Caching & Annex C.6

[Simon Wright <simon@pogner.demon.co.uk>]

In C.6 the AARM says

16 For a volatile object all reads and updates of the object as a
   whole are performed directly to memory.

   16.a Implementation Note: This precludes any use of register
      temporaries, caches, and other similar optimizations for that
      object.

We've been having an argument as to precisely what sort of "cache"
we're talking about here. Is it the CPU cache? does this imply that an
implementation must force a cache write-through for volatile objects?

My personal view is that the existence or otherwise of the cache is
transparent and that all that's required is that the write doesn't go
to registers. But then why does the AARM mention cache?

Are there (multi-processor, presumably) systems where you would have
to force a write-through to get the proper effect? Do Ada
implementations on such systems have to do that?

-- 
Simon Wright                        Work Email: simon.j.wright@gecm.com
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