From: Stephen Leake <stephen.a.leake.1@gsfc.nasa.gov>
Subject: Re: implementing software unsigned divide
Date: 10 May 2001 11:54:22 -0400
Date: 2001-05-10T16:09:50+00:00 [thread overview]
Message-ID: <u1ypx6vyp.fsf@gsfc.nasa.gov> (raw)
In-Reply-To: 3AF985BD.BC0E1C12@averstar.com
Tucker Taft <stt@averstar.com> writes:
> Does your chip happen to have 32-bits/16-bits => 16-bit
> quotient and 16-bit remainder?
No.
> For that case, clearly you just zero out the high order part rather
> than sign-extending to handle an unsigned dividend. If it has 32/32
> => 32, of course you can handle 16-bit unsigned trivially.
Yes, I got that part :).
I also realized (after your message yesterday) that if neither operand
has the high bit set, the signed divide will give the correct answer.
> A more general solution, I believe, is to (logical) shift both the
> dividend and divisor right 1 bit, do the divide, and then adjust the
> quotient up or down by 1 to get the remainder to be >= 0 and less
> than the divisor. (Obviously you need to first check for the special
> case when the divisor is <= 1!)
Ah, that sounds promising. Thanks!
--
-- Stephe
next prev parent reply other threads:[~2001-05-10 15:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-05-07 21:42 implementing software unsigned divide Stephen Leake
2001-05-08 6:04 ` Jacob Sparre Andersen
2001-05-08 7:44 ` Tarjei T. Jensen
2001-05-08 13:18 ` Ted Dennison
2001-05-08 15:24 ` Tucker Taft
2001-05-08 21:20 ` Stephen Leake
2001-05-09 18:00 ` Tucker Taft
2001-05-10 15:54 ` Stephen Leake [this message]
2001-05-13 23:17 ` Kenneth Almquist
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