From: "Dmitry A. Kazakov" <mailbox@dmitry-kazakov.de>
Subject: Re: Portable memory barrier?
Date: Mon, 8 May 2017 23:09:40 +0200
Date: 2017-05-08T23:09:40+02:00 [thread overview]
Message-ID: <oeqmqi$7ho$1@gioia.aioe.org> (raw)
In-Reply-To: enc2orF3oloU1@mid.individual.net
On 2017-05-08 22:29, Niklas Holsti wrote:
> On 17-05-08 19:22 , Dmitry A. Kazakov wrote:
>
> [snip]
>
>> I don't see anything there what would prevent CPU from changing the
>> order of accesses to two *independent* memory locations when only the
>> program logic ties them nothing else. Well, except that there is no
>> obvious reason why it would like to change that order.
>
> I quote from an earlier post of mine in this thread:
>
> Just as in C, volatile accesses in Ada are guaranteed to occur in the
> order and number written in the source code and executed in the
> "standard" order [moreover, this includes all tasks in the program]:
>
> RM C.6 (16/3): All tasks of the program (on all processors) that read or
> update volatile variables see the same order of updates to the
> variables.
This is ambiguous. Does it read as:
A. Order of updates per volatile variable
B. Order of updates to the set of all volatile variables
B is sufficient, A is not. Depending on the implementation A may imply B
or not.
--
Regards,
Dmitry A. Kazakov
http://www.dmitry-kazakov.de
next prev parent reply other threads:[~2017-05-08 21:09 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-06 2:23 Portable memory barrier? Jere
2017-05-06 8:47 ` Jeffrey R. Carter
2017-05-06 14:17 ` Jere
2017-05-06 19:08 ` Dennis Lee Bieber
2017-05-06 19:26 ` Jeffrey R. Carter
2017-05-06 19:41 ` Jeffrey R. Carter
2017-05-06 20:42 ` Niklas Holsti
2017-05-09 19:49 ` Randy Brukardt
2017-05-09 22:07 ` Jere
2017-05-11 1:14 ` Randy Brukardt
2017-05-10 18:28 ` Shark8
2017-05-11 1:17 ` Randy Brukardt
2017-05-11 16:23 ` Jeffrey R. Carter
2017-05-07 20:18 ` Robert Eachus
2017-05-08 7:45 ` Dmitry A. Kazakov
2017-05-08 15:56 ` Robert Eachus
2017-05-08 16:22 ` Dmitry A. Kazakov
2017-05-08 18:39 ` Robert Eachus
2017-05-08 19:18 ` Robert Eachus
2017-05-08 21:09 ` Dmitry A. Kazakov
2017-05-08 23:24 ` Robert Eachus
2017-05-09 0:30 ` Jere
2017-05-09 4:02 ` Robert Eachus
2017-05-09 4:32 ` Robert Eachus
2017-05-09 4:44 ` Robert Eachus
2017-05-09 22:26 ` Jere
2017-05-09 20:01 ` Randy Brukardt
2017-05-09 19:57 ` Randy Brukardt
2017-05-10 0:51 ` Jere
2017-05-10 5:25 ` J-P. Rosen
2017-05-10 22:56 ` Jere
2017-05-11 7:36 ` Dmitry A. Kazakov
2017-05-13 20:25 ` Jere
2017-05-10 7:13 ` Dmitry A. Kazakov
2017-05-10 16:45 ` Robert Eachus
2017-05-10 17:28 ` Simon Wright
2017-05-10 23:21 ` Jere
2017-05-11 0:47 ` Randy Brukardt
2017-05-13 20:11 ` Jere
2017-05-15 22:33 ` Randy Brukardt
2017-05-10 23:30 ` Jere
2017-05-11 0:38 ` Randy Brukardt
2017-05-10 16:38 ` Jeffrey R. Carter
2017-05-10 23:40 ` Jere
2017-05-10 16:19 ` Robert Eachus
2017-05-11 1:02 ` Randy Brukardt
2017-05-11 1:51 ` Robert Eachus
2017-05-15 22:45 ` Randy Brukardt
2017-05-08 20:29 ` Niklas Holsti
2017-05-08 21:09 ` Dmitry A. Kazakov [this message]
2017-05-09 4:34 ` Niklas Holsti
2017-05-09 6:16 ` Niklas Holsti
2017-05-09 8:34 ` Dmitry A. Kazakov
2017-05-09 20:18 ` Randy Brukardt
2017-05-09 20:10 ` Randy Brukardt
2017-05-09 0:05 ` Jere
2017-05-09 8:26 ` Dmitry A. Kazakov
2017-05-09 19:53 ` Randy Brukardt
2017-05-09 20:27 ` Dmitry A. Kazakov
2017-05-11 0:35 ` Randy Brukardt
2017-05-11 8:24 ` Dmitry A. Kazakov
2017-05-15 22:53 ` Randy Brukardt
2017-05-18 17:44 ` Dmitry A. Kazakov
2017-05-18 21:01 ` Randy Brukardt
2017-05-19 7:54 ` Dmitry A. Kazakov
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