Re: volatile vs aliased

[Simon Wright <simon@pushface.org>]

Martin Krischik <krischik@users.sourceforge.net> writes:

> Well, all machine code I have seen so far only have a INC for
> registers. And if you think for it for a sec.: It can't be another
> way, even if there is a INC for memory the CPU still has to read the
> memory increment internally write back.

On the other hand, there is a test-and-set instruction in many
architectures, isn't there? If the memory entity (byte?) is clear, set
it and succeed; if not, fail. This would presumably have to be done
using an uninterruptible read-modify-write cycle.

So it might be _possible_. But whether modern architectures actually
do it is another matter.

We recently had a problem where the BSP for our target board was
upgraded to make VME slave (exported) memory cachable by default. This
required so much in the way of bus snooping etc that if you accessed
the shared memory too often the card would freeze -- not good.