Re: initialize an array (1-D) at elaboration using an expression based on the index?

[Brian Drummond <brian_drummond@btconnect.com>]

On Sun, 31 Oct 2010 12:00:20 -0700 (PDT), Shark8 <onewingedshark@gmail.com>
wrote:

>> ... having been raised on Algol-W I am delighted to see them come back.
>>
>> Is it their unfamiliarity that disturbs you?
>
>No, not so much.
>I don't see how they are [strictly-speaking] necessary, given that we
>have declare-blocks (which can be arbitrarily-nested).
>Granted, they would make it a lot less verbose in many cases. {BTW, if
>we're going to allow if/then statements inside expressions &
>assignments/initializations then what's keeping us from using case-
>statements too?}

Nothing, as long as we can escape from expecting that all languages should look
like C...

>> They don't appear to have the same possibility for disaster as your C example,
>> and have been around in some form in VHDL for decades.
>
>That's quite true. However, I've learned to be careful around C/C++;
>they are full of little inconsistencies that the compiler will happily
>consume, 

Absolutely ... aaah, perhaps you have C's :? syntax in mind...
That makes me uncomfortable too, and it took me a long time to figure out why.

It's psychological; given the additional circumstances that booleans are
integers in C, I am strongly conditioned to expect the choices to be in
ascending order ( i.e. 0, 1, ... yet they are in descending order). 

Given that, I have always regarded C's ?: conditional operator as a poor
relation to if-expressions.
(I can still never read it correctly without stopping and thinking.)

Algol-W allows if- and case-expressions; as you suggest, there is no reason to
allow one and prohibit the other.

(approximate Ada syntax - untested!)

days := case month is
            feb => if leap(year) then 29 else 28;
            apr, jun, sept, nov =>30;
            others => 31;

>
>> (In the combinatorial/parallel part of the language. VHDL2008 reintroduces them
>> to the sequential part, inside processes)
>
>Interesting; what is the VHDL syntax for them, if I might ask?

A 2-way multiplexer can be written as

S <= A when SEL_A else B;

(A, B, SEL_A, S are signals, SEL_A is of type Boolean)
For this example I am using capitals for labels, lower case for keywords, but
VHDL is case-insensitive like Ada.

A 4-way multiplexer can be written as 

with SEL select
	S <= 	A when 0,
		B when 1,
		C when 2,
		D when 3,
		'Z' when others;

In this example, SEL is an integer signal. S and A..D are signals of a type
(std_logic) which allows a value 'Z' which means tristate or high impedance.
This means that S is undriven in the "others" case, and may be driven by some
other entity (not shown). Otherwise the example could have ended at 
"		D when others; " or even 
"		D when 3;" 
for which SEL should be an appropriately ranged integer type!

Signals in VHDL are (slightly) similar to Occam channels, or rendezvous between
Ada tasks, which are likewise similar to VHDL processes.

Thus the 2-way mux above is shorthand for

process (A,B,SEL_A);
begin
    if SEL_A then
      S <= A;
   else
      S <= B;
   end if;
end process;

This process wakes up on any event on any signal in its sensitivity list
(A,B,SEL_A, entries in Ada terms) and executes its sequential code until either
completion or a "wait" statement.

 In this case, the sequential code is merely a conditional statement and one of
two possible signal assignments. However it could use almost any sequential code
construct familiar from Ada. 

<= here denotes signal assignment, which can wake up other processes sensitive
to S. Processes can also have variables with the familiar := assignment; these
are only visible within the process, while signals connect between processes.

VHDL2008 allows the "when" and "select" forms in expressions within the
sequential code in processes. Why "when" and "select" when it uses "if" and
"case" to denote the equivalent statements, is a mystery to me...

- Brian