Re: Ariane 5 Failure from 1996

[John McCabe <john@nospam.assen.demon.co.uk.nospam>]

John McCabe <john@nospam.assen.demon.co.uk.nospam> wrote:

>FWIW though, if, as someone else has said, the SRI for  A5 used a
>MIL-STD-1750A processor then, as I remember that chip, there is a way
>for arithmetic overflow (i.e. x + y = z where x and y are both
>positive and z is negative) to cause a machine fault interrupt. I
>imagine that this would be disabled in C as it's not a check that
>should be made by the language (forgive me if my memory of
>MIL-STD-1750A is hazy, I haven't used them since 1997).

This is what I was getting at (from MIL-STD-1750A):

5.85 Convert floating point to 16-bit integer.
----------------------------------------
ADDR MODE MNEMONIC FORMAT/OPCODE
---- ---- -------- -------------
8 4 4
----------------------
R FIX RA,RB | E8 | RA | RB |
----------------------
DESCRIPTION: The integer portion of the floating point Derived
Operand, DO
----------- (i.e., the contents of registers RB and RB+1), is stored
into
register RA. If the actual value of the DO floating point exponent
is greater than 0F (Base 16), then RA remains unchanged and a
FIXED POINT OVERFLOW OCCURS. The condition status, CS, is set   <<<<<<
based on the result in RA.
Note: The algorithm truncates toward zero.

===============
Fixed point overflow is, I believe, a maskable interrupt.