Re: Thoughts and Opinions or something like that

[Ted Dennison<dennison@telepath.com>]

In article <HtiF6.5582$Tv2.757613@news6-win.server.ntlworld.com>, chris.danx
says...
>will complete this soon, but i've been thinking my approach is flawed.  Not to
>say RISC is bad, but maybe it's too simplistic or lacks specific support for
>features that'd make it A:more efficient and B:easier to program.

My memory from my architecture courses in college (maybe I'm no expert, but I
took that damn course 3 times...) on RISC is:

o  RISC is not *supposed* to be easy to program. Its supposed to give compiler
writers the minimal tools they will need. Programmers are supposed to use the
compilers, not RISC. If you are writing assembly language RISC code, you are
either writing a compiler, or you are fighting the system.

o  What is efficient depends on the rest of the architecture; particularly on
where the bottlenecks are. In this day and age, the bottleneck is in accessing
memory. Thus you want a lot of register-to-register instructions, and memory
accesses should be the last resort. Also, efficency requres that you "pipeline"
instructions, like on an assembly-line. Doing that, using hardware, without
having one in-progress instruction screw up another, is very complicated. To
make it achievable, you don't want to have lots of instructions, and you don't
want the ones you have to do very much.

Now the question you should be asking is, "Do these design goal make sense for
my virtual machine?" Unless you have an eye on making it an acutal machine, or
performing one-to-one transformations into the target platform's RISC code, I'd
guess the answer would be "no".

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