Re: simple CPUs, was Re: How Ada could have prevented the Red Code distributed denial of service attack.

["Marin David Condic" <dont.bother.mcondic.auntie.spam@[acm.org>]

Well, it typically isn't done to simplify timing estimates. Its done to be
sure that in the absolute worst case execution of the code, the timing
remains *predictable*. Rocket guys loathe things that aren't predictable
because they have enough unpredictabilities to deal with without throwing
timing uncertainties into the mix.

If you run through a routine in its worst case path and it takes N
milliseconds, you know that you aren't going to generate conditions under
which that is going to vary. Hence, when you pile all of the code together
and it runs worst case scenarios and you still have time left on the CPU
budget, you *know* that you aren't going to generate some sort of wierd
combination or permutation of execution paths that change this behavior.
Throw in cache and pipelining and then you've got to test the wierd
permutations to be sure you don't blow the CPU budget. That can range from
somewhere between extremely difficult to impossible - depending on your
scheduler.

Granted, if you have a CPU wherein you're only using 30% of the timing
budget under all of your tested conditions, you can probably do enough
analysis to figure out that the probability of any sort of cache or pipeline
combinations blowing the CPU budget is extremely low. But the metal benders
that tend to control deep space projects might not understand or accept
this - they like to deal with certainty. That and you seldom find yourself
with the luxury of running a state of the art microprocessor in the
gigahertz range - or if you did, it gets limited by the access speed of
memory or some other device. And even if you had 90% spare CPU budget, you
*know* that there's going to be someone who will find something to do with
it eventually - or tell you that the system is overbuilt and make you use a
cheaper part! :-)

But your point is taken - with many modern processors you could probably
eliminate the cache and pipelining and maybe do some other things to create
a more predictable (yet slower) device and still be coming out ahead. (I bel
ieve this was the idea behind the RH-32) The problem is that there aren't a
lot of silicon foundaries willing to make you a RAD-hard, custom version of
their chip (with all the required testing and certification) when the number
of chips you want to buy is measured in the hundreds.

MDC
--
Marin David Condic
Senior Software Engineer
Pace Micro Technology Americas    www.pacemicro.com
Enabling the digital revolution
e-Mail:    marin.condic@pacemicro.com
Web:      http://www.mcondic.com/


<tmoran@acm.org> wrote in message
news:sGhi7.17722$sa.8914739@news1.rdc1.sfba.home.com...
> >If Intel did offer some version of their 80x86 family in a deep-space,
> >...
> >One of the beauties of the 1750a was the indivisible nature
> >of the instructions, their simplicity and predictability. For
hard-realtime
>   I wonder how much performance loss there would be if you eliminated
> all the fancy pipelining etc etc from a Pentium IV, in order to simplify
> timing estimates?  As much as 1/2?  Continue to run at 1GHz, of course.