Re: Efficient Sequential Access to Arrays

[Keean Schupke <keean.schupke@googlemail.com>]

On Saturday, 21 July 2012 22:38:49 UTC+1, Dennis Lee Bieber  wrote:
> On Sat, 21 Jul 2012 09:14:11 -0700 (PDT), Keean Schupke declaimed the following in comp.lang.ada:
> 
> 
> > Here are my results:
> > 
> > 24 byte nodes (all integers) : 42k sims per second
> > 16 byte nodes (all short_ints) : 40k sims per second
> > 32 byte nodes (all integers + padding) : 42k sims per second.
> > 
> > So 32bit integers seem faster than 16bit integers, and as the whole data set fits in the cache (its less than 10kbytes) the size of the nodes does not really affect performance.
> >
> 	Presuming the computer has a 32-bit bus, those results are viable...
> The 16-bit data may require loading 32-bit words followed by shifting
> and/or masking the undesired part.
> -- 
> 	Wulfraed                 Dennis Lee Bieber         AF6VN

The CPU is 64bits wide, the cache lines are 64 bytes long. The CPU is connected to the cache by a bus much wider than 64 bits (512 bits I think) and the cache is several megabytes so the working set easily fits in the bus. The main memory controller has multiple channels operating at 32 bit width but clocked independently of the processor so it is better to think in terms of memory bandwidth and page-miss cost of the DRAM.


Cheers,
Keean.