Re: AI12-0218: What is the portable representation clause for processing IETF packets on little-endian machines?

["Dan'l Miller" <optikos@verizon.net>]

On Thursday, May 10, 2018 at 12:45:43 PM UTC-5, Dan'l Miller wrote:
> … byte-swapping is what makes the Internet work on the computer that you are using right this instant
> (unless you are using a PowerPC-, POWER-, 68K-, MIPS-, or mainframe-based computer or an Alpha- or
> Itanium-based computer configured in the rare big-endian configuration).

Oops.  In that list, I forgot SPARC there for another 0.01%* of the computers on planet Earth.

* I am completely uncertain whether that is hyperbole or fact.  I pulled that number out of thin air, but it sounds about right.

And just in case anyone is thinking, “Oh, every single one of the new designs of ISAs have been big-endian for decades; all those little-endian ISAs are all for antiquated legacy reasons:  ARM derived from little-endian 6502; Alpha derived from little-endian VAX; Intel derived from Fairchild”, the newest (open-source!) hot-shot kid on the block in the ISA neighborhood is •little-endian•:  RISC-V.

https://en.wikipedia.org/wiki/RISC-V

RISC-V looks promising too, likely to give PowerPC, MIPS, SPARC, and ARM a run for their money.  Here is Esperanto's debut RISC-V product, which as a leap forward has practically no direct competitor in any other ISA:
https://fuse.wikichip.org/news/686/esperanto-exits-stealth-mode-aims-at-ai-with-a-4096-core-7nm-risc-v-monster