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From: Robert Dewar <robert_dewar@my-deja.com>
Subject: Re: Help with Atomic_Components and whole array assignment
Date: Tue, 30 Jan 2001 18:20:20 GMT
Date: 2001-01-30T18:20:20+00:00	[thread overview]
Message-ID: <9570ko$fg1$1@nnrp1.deja.com> (raw)
In-Reply-To: 3A76E3B9.BD806841@averstar.com

In article <3A76E3B9.BD806841@averstar.com>,
  Tucker Taft <stt@averstar.com> wrote:
> I don't agree with Robert's reading of this.  It seems very
> clear that you cannot combine multiple updates of separate
> atomic objects into a single write.

I disagree with Tuck. Please provide a test program where it
would be theoretically possible to determine that combining
writes had a semantic effect.

> One of the whole points of atomic
> is to make each write separate and indivisible.

Indivisible, yes. Separate no. You may have intended to say
this, and you may have thought it, but I don't see that the
RM says, or even implies this.

> It was designed specifically to address issues relating to
> "active" memory, where breaking the write down into multiple
> writes, or combining multiple writes into a single write,
> would confuse the device.

This is a total surprise to me, and certainly there is nothing
in the RM that would reveal this hidden design intent. For
example, an implementation which locks the bus and then does
a whole sequence of writes for an atomic variable, and then
unlocks the bus, CLEARLY meets the semantics of the RM.

This is a case of the designer reading more into what's there
than what was written. My own view is that it is almost
impossible to achieve the design goal that Tuck quotes, except
on an implementation advice basis. I had no idea that the
design team had this view of pragma Atomic (because nothing
they ever wrote in the RM implied this viewpoint).

Note that the detailed list in AARM C.6(20) of disallowed
transformations has no hint at all of the "separate" part of
Tuck's claim, and conspicuously does not list combining writes
as an improper transformation.

Tuck, having something in your mind is not good enough if you
do not write it down :-)

> In general, that means each read/update is a separate
> instruction.

No, there is absolutely NO implication of this

> Which particular instruction is not specified, though of
> course in most cases it will be a load or a store.

> I don't agree with the advice of slipping into machine code
> to accomplish all of these kinds of things, if atomic can do
> the job.

But it can't! In particular, suppose you have four atomic
byte variables next to one another. It is perfectly fine to
do a word load followed by a shift and mask, but likely this
would play havoc with memory mapped I/O.


> I would agree that with the original code, which used an
> aggregate assignment, there is no requirement to perform that
> as separate byte assignments.  However, if the code is
> written as a sequence (or a loop) of separate assignments,
> and the objects are atomic, it is a bug (in my view) if the
> compiler combines these assignments  into a single
> assignment.

You repeat this, but the RM does not support this view point.

> Similarly, reordering such assignments
> would be a bug, since it would change the external effect of
> the program in an impermissible way.

No, this is not similar at all. Everyone agrees that reordering
is not permitted, because you can see external effects not
corresponding to the canonical order. The RM is quite explicit
in this case, and indeed AARM C.6(20.c) gives an explicit
example of this not being allowed, but the AARM does not list
combining.

Too bad you did not list the combining case in the AARM Tuck,
then we would at least have known what was in your mind, and
could have discussed the point that the RM wording does not
happen to capture this intent (and as I say, I think it would
be almost impossible to capture this intent).

For all the examples in AARM C.6(20), you can devise simple
pure Ada tests that can conceptually malfunction because of
a task switch at a bad point (it may be tricky to actually
do the run that fails, since it depends on very precise
timing). But for the combining case, you cannot devise a
pure Ada test that even conceptually fails.

The idea that pragma Atomic solves this problem is an old
confusion, going way back to Ada 83 days, I thought we had
put that to rest in Ada 95, because we never discussed the
idea that Atomic *did* solve this problem. I am somewhat
amazed to see the claim that it was addressed :-)



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  reply	other threads:[~2001-01-30 18:20 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2001-01-22 11:22 Help with Atomic_Components and whole array assignment r_c_chapman
2001-01-22 12:51 ` Stuart Palin
2001-01-22 14:16   ` mark_lundquist
2001-01-22 16:09     ` Pat Rogers
2001-01-22 16:29     ` Robert Dewar
2001-01-22 19:52       ` Mark Lundquist
2001-01-30 15:54       ` Tucker Taft
2001-01-30 18:20         ` Robert Dewar [this message]
2001-01-31  5:08           ` DuckE
2001-01-31  5:57             ` Robert Dewar
2001-02-01  3:31               ` DuckE
2001-02-02 21:38               ` Mark Lundquist
2001-02-02 23:08                 ` Robert Dewar
2001-02-03  1:39                 ` tmoran
2001-01-22 16:21 ` Robert Dewar
2001-01-22 16:39   ` r_c_chapman
2001-01-30 15:57     ` Tucker Taft
2001-01-30 18:26       ` Robert Dewar
2001-01-30 21:30         ` Simon Wright
2001-02-01  6:11           ` Robert Dewar
2001-02-06  0:32         ` Richard Kenner
2001-02-06  3:15           ` Robert Dewar
2001-01-31 10:09       ` Rod Chapman
2001-01-31 21:41         ` Tucker Taft
2001-02-01  5:33           ` Robert Dewar
2001-02-01  9:42           ` Rod Chapman
2001-02-01 18:10             ` Robert Dewar
2001-02-01 13:14           ` SPARK flow analysis (was Help with Atomic_Components and whole array assignment) Stuart Palin
2001-02-01 23:38           ` Help with Atomic_Components and whole array assignment Nick Roberts
2001-02-02  3:45             ` Robert Dewar
2001-02-07 21:40           ` Nick Williams
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