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From: Robert Dewar <robert_dewar@my-deja.com>
Subject: Re: Caching & Annex C.6
Date: 1999/09/05
Date: 1999-09-05T00:00:00+00:00	[thread overview]
Message-ID: <7qss9f$a19$1@nnrp1.deja.com> (raw)
In-Reply-To: x7vyaenahw3.fsf@pogner.moho

In article <x7vyaenahw3.fsf@pogner.moho>,
  Simon Wright <simon@pogner.demon.co.uk> wrote:
> Are there (multi-processor, presumably) systems where you
would have
> to force a write-through to get the proper effect?

yes

 Do Ada
> implementations on such systems have to do that?

yes

The point is that for non-volatile objects, which you know
cannot be shared variables in the Ada sense, it is safe
to put them in cache, even if the cache is non-coherent,
but the point is that Volatile prevents this "optimization".

Machines with non-coherent caches always have a way of
signalling selected data as being non-cachable, forcing
access to a shared memory (well let's say, that's true
of shared memory machines).



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  reply	other threads:[~1999-09-05  0:00 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
1999-09-03  0:00 Caching & Annex C.6 Simon Wright
1999-09-05  0:00 ` Robert Dewar [this message]
1999-09-05  0:00   ` Simon Wright
1999-09-07  0:00 ` David Kristola
1999-09-08  0:00   ` Robert Dewar
1999-09-08  0:00     ` David Kristola
1999-09-08  0:00       ` Robert Dewar
1999-09-09  0:00         ` Memory mapped registers (was Re: Caching & Annex C.6) David Kristola
1999-09-09  0:00           ` Robert Dewar
1999-09-14  0:00             ` Memory mapped registers (was Re: Cachi David Kristola
1999-09-14  0:00               ` Robert Dewar
1999-09-15  0:00                 ` David Kristola
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