Ravenscar-sfp and interrupt priorities on Cortex-M4

[Patrick Noffke <patrick.noffke@gmail.com>]

Hello,

I am porting the GNAT Ravenscar-sfp runtime to work with the TI TM4C MCU, using the STM32F4 implementation as a starting point.

I noticed a problem where the interrupt priorities were not correct.  I was setting an interrupt handler's priority to 251, and the runtime converted it to a PRI value, and when it got converted back to an Interrupt_Priority it came back as 252.

I determined this is because the TM4C MCU only uses the 3 most-significant bits for the PRI value, where as the runtime implementation assumes 4 bits.  The ARM Cortex-M4 user's guide does not specify the number of bits, only that the most significant bits shall be used and the unused bits are zeros when read and writes have no effect (http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/CIHIGCIF.html).

The file system-xi-cortexm4-sfp.ads defines Interrupt_Priority range from 241 to 255, and this should be 249 to 255 for the TM4C MCU.  Because the available range is processor-dependent, this file should probably be renamed to something like system-xi-stm32f4.ads and system-xi-tm4c.ads, etc., and the appropriate file selected in build-rts.sh.

I copied file s-bbbosu-stm32f4.adb to s-bbbosu-tm4c.adb and had to then change the To_PRI and To_Priority functions to multiply and divide by 32, respectively.

I am happy to share my implementation when I have confidence it is working.  Please let me know the best way to share it.  I'm fine for it to become a part of the GNAT release.

Please let me know if you agree with my above findings and suggestions.

Best regards,
Patrick