Re: Expected bytes per sloc (semicolons) performance

[dewar@gnat.com (Robert Dewar)]

"Jeff Creem" <jeff@thecreems.com> wrote in message news:<_hRp7.7630$ot.1153235@typhoon.ne.mediaone.net>...
> As for RISC/CISC.... One sometimes ends up with slightly larger code on a
> RISC than
> CISC machine but this probably has almost as much to do with mandatory nops,
>  missed delayed branch opportunities and alignment requirements as it does
> with
> the straight RISC/CISC issues.

This is a misleading assessment. First of all most modern
RISC machines do not have mandatory nops etc, so you are
really talking about old style architectures here.

Second, these days CISC in practice means ia32 (and we
now include x86-64) and the code for this architecture 
is significantly more compact, not just slightly. And
the reasons are not the ones you gave above, but rather
that this architecture has many short instructions, e.g.
normal references to the local frame are 2-byte instructions instead
of 4-bytes, as are most conditional
jumps and normal register/register arithmetic. This can
add up to a big and significant difference, which can
translate into significant icache advantages. This is one
of the reasons that this architecture does "better than
expected" when compared to RISC designs.