ADA - VHDL

ADA - VHDL

[P. Cnudde VH14 (8218)]

Hello,

As a "experienced" VHDL programmer and now looking for the
first time really into ADA I have some historical questions
and I hoped that somebody on those two newsgroups could help me
making some points more clear.

I agree there are a lot of similarities between the languages, but I do
not understand the reason for many differences. There are things which 
I can not do in VHDL which I can in ADA and for which I see no reason.
 some examples: 
	type new Integer;
	generics;
	variant records

on the other hand there are also points which are more flexible in VHDL
	
I also see no reason for some syntax differences ("to" in VHDL, ".." in ADA)

I agree the differences may be small but to my oppinion it will cause problems
in the future where hardware-software codesign will come a reallity and a single
language we be needed. I think that VHDL-ADA is a very powerfull combination but
would it not be possible to get the small differences between the languages out of 
way and grow to a single language capable of discribing both: VHDL-ADA-2000

What are the oppinions of the experts on this point?


Regards,


-- 


   ___________          Peter Cnudde
  _\         /_         Alcatel Bell Telephone
  \ \ALCATEL/ /         Switching Systems Division 
   \ \ BELL/ /          Microelectronics Design Center
    \ \   / /           
     \ \ / /            F. Wellesplein 1, B-2018 Antwerp
      \ Y /                                      BELGIUM
       \|/              e-mail  : cnuddep@sh.bel.alcatel.be
        *               Phone   : (32/3) 240 82 18
                        Fax     : (32/3) 240 99 47

Re: ADA - VHDL

[Jacques Rouillard]

In article <31E2391F.A16BEBD@sh.bel.alcatel.be>, "P. Cnudde VH14 (8218)"
<cnuddep@sh.bel.alcatel.be> wrote:

> Hello,
> 
> As a "experienced" VHDL programmer and now looking for the
> first time really into ADA I have some historical questions
> and I hoped that somebody on those two newsgroups could help me
> making some points more clear.
> 
> I agree there are a lot of similarities between the languages, but I do
> not understand the reason for many differences. There are things which 
> I can not do in VHDL which I can in ADA and for which I see no reason.
>  some examples: 
>         type new Integer;

You're right that you can have integer types in VHDL but you can't have a
new integer. I think the main reason is complexity.

>         generics;

Ibidem. Genericity in Ada is an order of magnitude more complex than in VHDL.

>         variant records

Here there is a fundamental reason: signals are defined based on
scalarity. The very notion of event is at risk if you have variant
records. This was examined in a special session of the ballot resolution
group, and the only workable solution led to a separation of the notion of
scalar type (which you can't cut into parts) from atomic type (of which
you can make a signal). Abandonned because of complexity.

> 
> on the other hand there are also points which are more flexible in VHDL
>         
> I also see no reason for some syntax differences ("to" in VHDL, ".." in ADA)
> 

In Ada you don't have downtos which were felt a must when you have to deal
with hardware busses.


> I agree the differences may be small but to my oppinion it will cause problems
> in the future where hardware-software codesign will come a reallity and
a single
> language we be needed. I think that VHDL-ADA is a very powerfull
combination but
> would it not be possible to get the small differences between the
languages out of 
> way and grow to a single language capable of discribing both: VHDL-ADA-2000
> 
> What are the oppinions of the experts on this point?

Unfortunatly IMHO the two languages have diverged to a point that a
VHDL-ADA is not realistic. The similarities between the two languages are
a danger more than a clue, most of the time.

-- Jacques Rouillard 
USA http://vhdl.org/~rouillard   EU http://ismea.imt-mrs.fr/~rouillar

Re: ADA - VHDL

[Paul B. Graham]

> I also see no reason for some syntax differences ("to" in VHDL, ".." in ADA)

VHDL has ascending and descending ranges.  Ada has only ascending ranges.
I find it more convenient and understandable to write, e.g.,

	for i in 10 downto 1 loop	-- VHDL

than

	for i in reverse 1 .. 10 loop	-- Ada

Paul

Re: ADA - VHDL

[Laurent Gasser]

In article <4s09jq$ddn@srvr1.engin.umich.edu>, pbgraham@engin.umich.edu (Paul B. Graham) writes:
> > I also see no reason for some syntax differences ("to" in VHDL, ".." in ADA)
> 
> VHDL has ascending and descending ranges.  Ada has only ascending ranges.
> I find it more convenient and understandable to write, e.g.,
> 
> 	for i in 10 downto 1 loop	-- VHDL
> 
> than
> 
> 	for i in reverse 1 .. 10 loop	-- Ada
> 
> Paul

In Ada, the range of the loop can be given by a type.
 
   for i in reverse Weekdays loop 
   
I don't know VHDL at all. Is anything similar in VHL possible?

-- 
Laurent Gasser (lga@sma.ch)
Computers do not solve problems, they execute solutions.

Re: ADA - VHDL

[P. Cnudde VH14 (8218)]

Laurent Gasser wrote:
> 
> In Ada, the range of the loop can be given by a type.
> 
>    for i in reverse Weekdays loop
> 
> I don't know VHDL at all. Is anything similar in VHL possible?

There exist an attribute 'reverse_range
which can be used to get the same result.




> 
> --
> Laurent Gasser (lga@sma.ch)
> Computers do not solve problems, they execute solutions.

-- 


   ___________          Peter Cnudde
  _\         /_         Alcatel Bell Telephone
  \ \ALCATEL/ /         Switching Systems Division 
   \ \ BELL/ /          Microelectronics Design Center
    \ \   / /           
     \ \ / /            F. Wellesplein 1, B-2018 Antwerp
      \ Y /                                      BELGIUM
       \|/              e-mail  : cnuddep@sh.bel.alcatel.be
        *               Phone   : (32/3) 240 82 18
                        Fax     : (32/3) 240 99 47

Re: ADA - VHDL

[Paul B. Graham]

> >    for i in reverse Weekdays loop
> 
> There exist an attribute 'reverse_range
> which can be used to get the same result.

Actually not.  The 'RANGE and 'REVERSE_RANGE attributes in VHDL can only
be used with array types.  Thus in Ada you can write

    for i in character loop ...
or
    for i in reverse character loop ...

But in VHDL you must do

    for i in character loop
or
    for i in character'high downto character'low loop

because the construct

    for i in character'reverse_range loop

is illegal.

Paul

Re: ADA - VHDL

[Robert Dewar]

Paul says

"VHDL has ascending and descending ranges.  Ada has only ascending ranges.
I find it more convenient and understandable to write, e.g.,

        for i in 10 downto 1 loop       -- VHDL

than

        for i in reverse 1 .. 10 loop   -- Ada

Paul
"

Unconvincing -- sure you will always find someone who finds X more
"convenient and understandable" than Y (and of course someone else
who finds Y more "convenient and understandable" than X). I do not
find this a good basis for a gratuitous change like the above (I
would find a change in either direction gratuitious), and indeed
it seems that some of the differences between VHDL and Ada are
not justified, they seem to be cases where personal taste has
intruded unnecessarily.

Re: ADA - VHDL

[Michael Feldman]

In article <dewar.837036283@schonberg>, Robert Dewar <dewar@cs.nyu.edu> wrote:

>Paul says
>"VHDL has ascending and descending ranges.  Ada has only ascending ranges.

>Unconvincing -- sure you will always find someone who finds X more
>"convenient and understandable" than Y (and of course someone else
>who finds Y more "convenient and understandable" than X). I do not
>find this a good basis for a gratuitous change like the above (I
>would find a change in either direction gratuitious), and indeed
>it seems that some of the differences between VHDL and Ada are
>not justified, they seem to be cases where personal taste has
>intruded unnecessarily.

An important point here is that the ascending range syntax allows
a named range to be used for counting either up or down:

  type Days is (Mon, Tue, Wed, Thu, Fri, Sat, Sun);

(or any integer range as well; I just like enumerations:-))

Going forward in the week,  one can just write

  for Day in Days loop...

going backward, one can just write

  for Day in reverse Days loop...

The real advantage here is that you can avoid "magic numbers" in
your code, so that if - to carry my stupid Days example further -
we changed the enumeration values to French ones -

  type Days is 
    (lundi, mardi, mercredi, jeudi, vendredi, samedi, dimanche);

the rest of your code is unchanged.

We could even declare an array type

  type Weekly_Pay is array (Days) of Float; (say)

and an object

  ThisWeek: Weekly_Pay;

and the array index, the forward loop, and the backward loop, are all
consistent and immune from inconsistent code changes.

This is a real improvement over the Pascal loop syntax, which VHDL 
borrowed and which has no way to use the named range.

Ada syntax is remarkably regular in this regard.

(Yes, I know - there's no "by" field in an Ada for statement.
No free lunch.:-))

Mike Feldman

Re: ADA - VHDL

[Robert Dewar]

Peter said

"I agree there are a lot of similarities between the languages, but I do
not understand the reason for many differences. There are things which
I can not do in VHDL which I can in ADA and for which I see no reason.
 some examples:
        type new Integer;
        generics;
        variant records"

These are all fundamental features of Ada that provide very important
expressive power (I don't know VHDL well enough to comment on how it
can manage without these critical features, or how one works around
the absence).

Probably the easiest way to understand these features is to read a book
like Barnes, although the original Ada 83 rationale is also a good souce
of information if you want to concentrate on the *why* rather than the *what*.

Very briefly:

  derived types allow separation of type spaces (new integer for example
  generates a type different from integer, so that the compiler can check
  improper operations like assigning a temperature to a distance.

  generics are a fundamental feature in any language. C++ at first lacked
  this capability, and it was added in the form of templates. There are
  many things that generics do, but most critically they allow type
  parametrization of reusable components.

  variant records are discriminanted unions, as found in say Pascal. Some
  kind of union facility is essential if you have recursive data structures
  (to end the recursion if it ends in a different type).

Re: ADA - VHDL

[Brian "Cheebie" Merchant]

Let the log show that Robert Dewar wrote:

>Peter said
>
>"I agree there are a lot of similarities between the languages, but I do
>not understand the reason for many differences. There are things which
>I can not do in VHDL which I can in ADA and for which I see no reason.
> some examples:
>        type new Integer;
>        generics;

Unless there is a nomenclature problem, VHDL has these.  I use them
often.

>        variant records"

As for the other two.  VHDL is, in the end, a way to describe
*hardware*.  There are some extremely useful software construct which
simply do not translate well to hardware.  (recursive structures is one
of these)

---
cheebie@smart.net
The Mighty Cheebie: loyal drone in the service of Da Queen
Eater of Oreos, wearer of wing weaves, maker of pillows.

Re: ADA - VHDL

[P. Cnudde VH14 (8218)]

Brian Cheebie Merchant wrote:
>    There are some extremely useful software construct which
> simply do not translate well to hardware.  (recursive structures is one
> of these)

I would disagree on the point of recursion. I try to make my function calls
in VHDL recursive if it is possible. To my oppinion it generates far better
hardware in general. 

 An example:

   -- Calculate Parity bits
   function HasEvenParity(constant Argument : in bit_vector) 
      return boolean is
      constant High   : integer := Argument'high;
      constant Low    : integer := Argument'low;
      constant Length : integer := Argument'length;
   begin
      if Length=1 then
         return not BitToBoolean(Argument(High));
      else
         return (HasEvenParity(Argument(High downto (High+Low+1)/2))
                 = HasEvenParity(Argument((High+Low-1)/2 downto Low)));
      end if;
   end HasEvenParity;

This generates a very efficient hardware realisation. In software on the other
hand I would NOT use recursion here. (due to function call overhead). 

(Of course when you use recursion you must make sure that the recursion
depth is fixed).


Regards,



-- 


   ___________          Peter Cnudde
  _\         /_         Alcatel Bell Telephone
  \ \ALCATEL/ /         Switching Systems Division 
   \ \ BELL/ /          Microelectronics Design Center
    \ \   / /           
     \ \ / /            F. Wellesplein 1, B-2018 Antwerp
      \ Y /                                      BELGIUM
       \|/              e-mail  : cnuddep@sh.bel.alcatel.be
        *               Phone   : (32/3) 240 82 18
                        Fax     : (32/3) 240 99 47

Re: ADA - VHDL

[jos de laender vh14 7461]

In article <31ead866.2979882@news.smart.net>, cheebie@sexy.and.smart.net
(Brian "Cheebie" Merchant) writes:
|> 
|> As for the other two.  VHDL is, in the end, a way to describe
|> *hardware*.  There are some extremely useful software construct
which
|> simply do not translate well to hardware.  (recursive structures is
one
|> of these)

	No it isn't. Not all software constructs are at now 
	translated efficiently to hardware, but that's merely 
	a matter of time. 
	Recursive structures ARE translated now to hardware (at
	least by Synopsys).

ir. Jos De Laender
VLSI design
Alcatel Telecom, Antwerp

|> 
|> ---
|> cheebie@smart.net
|> The Mighty Cheebie: loyal drone in the service of Da Queen
|> Eater of Oreos, wearer of wing weaves, maker of pillows.

Re: ADA - VHDL

[Stephen A. Bailey]

>>There are things which
>>I can not do in VHDL which I can in ADA and for which I see no reason.
>> some examples:
>>        type new Integer;
>>        generics;
>Unless there is a nomenclature problem, VHDL has these.  I use them
>often.

True.  You don't need to say "new"; simply:

    type New_int is range <integer range>;

Also, generics are limited to entities and blocks.  (Something Ada
does not have.)  The original statement probably referred to their
omission from packages in VHDL.

>>        variant records"
>
>As for the other two.  VHDL is, in the end, a way to describe
>*hardware*.  There are some extremely useful software construct which
>simply do not translate well to hardware.  (recursive structures is one
>of these)

The main issue with variant records is how they translate into
events/transactions for signals declared to be of a variant record
type (or a type containing such a subelement).  VHDL semantics break
composite signals down to the scalar level.

VHDL does allow recursive structures via generates and component
instantiations.


===========================================================
Stephen A. Bailey             pager: 408.271.7048
                              voice: 408.271.7048
850 Saratoga Ave, Apt E-106
San Jose, CA 95129
email: stephen@srbailey.com   http:  www.srbailey.com
===========================================================

Re: ADA - VHDL

[Nick Weavers]

Brian Cheebie Merchant wrote:

> As for the other two.  VHDL is, in the end, a way to describe
> *hardware*.  

This doesn't rule out having higher levels of abstraction
to support complex simulation testbenches. The full power of
a software language can surely be exploited here, particularly
some of the OO concepts. 

-- 
Nick Weavers, IBM Sub Systems Development, IBM UK Ltd, Langstone Road,
PO Box 6, Havant, Hampshire PO9 1SA, England, UK
Tel: 011-44-(0)1705-486363 ext 5121  Fax: Fax 011-44-(0)1705-499278
Email: weav@hursley.ibm.com

Re: ADA - VHDL

[Jean-Marc Bourguet]

dewar@cs.nyu.edu (Robert Dewar) writes
> 
> Paul says
> 
> "VHDL has ascending and descending ranges.  Ada has only ascending ranges.
> I find it more convenient and understandable to write, e.g.,
> 
>         for i in 10 downto 1 loop       -- VHDL
> 
> than
> 
>         for i in reverse 1 .. 10 loop   -- Ada
> 
> Paul
> "
> 
> Unconvincing -- sure you will always find someone who finds X more
> "convenient and understandable" than Y (and of course someone else
> who finds Y more "convenient and understandable" than X). I do not
> find this a good basis for a gratuitous change like the above (I
> would find a change in either direction gratuitious), and indeed
> it seems that some of the differences between VHDL and Ada are
> not justified, they seem to be cases where personal taste has
> intruded unnecessarily.
> 

I think this difference between VHDL and Ada is perhaps gratuitous,
but has the advantage to emphasize the difference between VHDL and
Ada range. VHDL range are characterized by
	- base type
	- bounds
	- direction
when Ada range are characterized by 
	- base type
	- bounds

So the downto in the VHDL instruction is part of the syntax of the
range, and may be used everywhere a range is needed (indexes of array
by example) when the reverse in the Ada equivalent is part of the
syntax of the loop.

As a consequence, VHDL has attribute Left, Right, Low, High to get the
bounds of the range, and Ascending to know its direction where Ada has
only (and need only) First and Last.

I wonder if descending range would be used so much if we had to write
	signal Data is std_logic_vector (reverse 0..7);
-- 
 Jean-Marc Bourguet                      Service d'Electronique
                                         Faculte polytechnique de Mons
 Email : bourguet@muelec.fpms.ac.be      Mons, Belgique

Re: ADA - VHDL

[Jens Hansson]

In article <31E2391F.A16BEBD@sh.bel.alcatel.be>, cnuddep@sh.bel.alcatel.be 
says...
>
>Hello,
>
>As a "experienced" VHDL programmer and now looking for the
>first time really into ADA I have some historical questions
>and I hoped that somebody on those two newsgroups could help me
>making some points more clear.
>
>I agree there are a lot of similarities between the languages, but I do
>not understand the reason for many differences. There are things which 
>I can not do in VHDL which I can in ADA and for which I see no reason.
> some examples: 
>        type new Integer;
>        generics;
>        variant records
>
>on the other hand there are also points which are more flexible in VHDL
>        
>I also see no reason for some syntax differences ("to" in VHDL, ".." in ADA)
>
>I agree the differences may be small but to my oppinion it will cause problems
>in the future where hardware-software codesign will come a reallity and a 
single
>language we be needed. I think that VHDL-ADA is a very powerfull combination 
but
>would it not be possible to get the small differences between the languages 
out of 
>way and grow to a single language capable of discribing both: VHDL-ADA-2000
>
>What are the oppinions of the experts on this point?

Disclaimer: I don't consider myself to be an expert in neither Ada nor VHDL.

Does it make sense to have the same syntax for languages with this big 
differences in semantics? A program written to be very efficient in Ada 
may be impossible or at least very inefficient to synthesize in VHDL. The 
opposite is valid as well.

Netlists (Port maps) could be used in a data driven computer architecture, but 
there are few (if any) commercial computers working this way. Timing has no 
meaning in Ada, while it is essential in VHDL, both regarding clock cycles and 
physical timing.

If you want to speed up software, decrease the number of instructions that are 
to be executed. Lots of these optimisations can be done automatically.

If you want to speed up hardware (essentially), multiply the hardware and/or 
pipeline the architecture. This changes system timing (in #clocks) and uses 
more expensive resources (area or gates), and therefore must be controlled to a 
greater extent by the "programmer".

Just my 2cents worth...

--Jens

Re: ADA - VHDL

[Jean-Marc Bourguet]

mfeldman@seas.gwu.edu (Michael Feldman) writes
> 
> In article <dewar.837036283@schonberg>, Robert Dewar
> <dewar@cs.nyu.edu> wrote:
> 
> >Paul says
> >"VHDL has ascending and descending ranges.  Ada has only 
> >ascending ranges.
> 
> >Unconvincing -- sure you will always find someone who finds X more
> >"convenient and understandable" than Y (and of course someone else
> >who finds Y more "convenient and understandable" than X). I do not
> >find this a good basis for a gratuitous change like the above (I
> >would find a change in either direction gratuitious), and indeed
> >it seems that some of the differences between VHDL and Ada are
> >not justified, they seem to be cases where personal taste has
> >intruded unnecessarily.
> 
> An important point here is that the ascending range syntax allows
> a named range to be used for counting either up or down:
> 
>   type Days is (Mon, Tue, Wed, Thu, Fri, Sat, Sun);
> 
> (or any integer range as well; I just like enumerations:-))
> 
> Going forward in the week,  one can just write
> 
>   for Day in Days loop...
> 
> going backward, one can just write
> 
>   for Day in reverse Days loop...

In VHDL a range include a direction. So you can write
	for Day in Days'High downto Days'Low loop
to go backward (Days may be declared as an ascending or descending
range). You may use
	for Day in Days'Right downto Days'Left loop
if you know that the Days range is ascending.

If you want to go in the reversed direction of Days but do not know
apriori if Days is an ascending or descending range, you may
have to use a test
	if Days'Ascending then
	  for Day in Days'Right downto Days'Left loop
	    ...
	  end loop;
	else
	  for Day in Days'Right to Days'Left loop
	    ..
	  end loop;
	end if;
but more probably the Day variable is use to index an array
(Weekly_Pay). Then you can be independent of the type of the index of
Weekly_Pay and write
	for Day in Weekly_Pay'Range loop
for the declared direction, and
	for Day in Weekly_Pay'Reverse_Range loop
for the reversed direction. (VHDL miss a Reversed attribute that
may be applied to range type...)

> The real advantage here is that you can avoid "magic numbers" in
> your code, so that if - to carry my stupid Days example further -
> we changed the enumeration values to French ones -
> 
>   type Days is 
>     (lundi, mardi, mercredi, jeudi, vendredi, samedi, dimanche);
> 
> the rest of your code is unchanged.
> 
> We could even declare an array type
> 
>   type Weekly_Pay is array (Days) of Float; (say)
> 
> and an object
> 
>   ThisWeek: Weekly_Pay;
> 
> and the array index, the forward loop, and the backward loop, are all
> consistent and immune from inconsistent code changes.
> 
> This is a real improvement over the Pascal loop syntax, which VHDL 
> borrowed and which has no way to use the named range.

This is what confuse you: VHDL didn't borrow the Pascal loop syntax,
but extented the notion of range in Ada to add a direction to the
range characteristic. You can define subtype of Days
	subtype Forward_Days is Days range lundi to dimanche;
	subtype Backward_Days is Days range dimanche downto lundi;
and use these subtype as index to an array.

> Ada syntax is remarkably regular in this regard.

VHDL syntax also (but miss the reversed attribute on a range but I
wonder if it has practical effect. I don't see any application where
you don't know the direction of a range, exept when used to constrain
the index of an unconstrained index.)

> (Yes, I know - there's no "by" field in an Ada for statement.
> No free lunch.:-))
> Mike Feldman

-- 
 Jean-Marc Bourguet                      Service d'Electronique
                                         Faculte polytechnique de Mons
 Email : bourguet@muelec.fpms.ac.be      Mons, Belgique

Re: ADA - VHDL

[Michael Feldman]

In article <sgvifuq6ot.fsf@su2>,
Jean-Marc Bourguet  <bourguet@muelec.fpms.ac.be> wrote:

>This is what confuse you: VHDL didn't borrow the Pascal loop syntax,
>but extented the notion of range in Ada to add a direction to the
>range characteristic. You can define subtype of Days
>	subtype Forward_Days is Days range lundi to dimanche;
>	subtype Backward_Days is Days range dimanche downto lundi;
>and use these subtype as index to an array.

Ah, you are right - I missed this. Thanks for the correction.

Mike Feldman
------------------------------------------------------------------------
Michael B. Feldman -  chair, SIGAda Education Working Group
Professor, Dept. of Electrical Engineering and Computer Science
The George Washington University -  Washington, DC 20052 USA
202-994-5919 (voice) - 202-994-0227 (fax) 
http://www.seas.gwu.edu/faculty/mfeldman
------------------------------------------------------------------------
       Pork is all that money the government gives the other guys.
------------------------------------------------------------------------
WWW: http://lglwww.epfl.ch/Ada/ or http://info.acm.org/sigada/education
------------------------------------------------------------------------

Re: ADA - VHDL

[Chris Papademetrious]

"P. Cnudde VH14 (8218)" <cnuddep@sh.bel.alcatel.be> wrote:
>	generics;

 Actually, VHDL does support generics.  I used them quite extensively
for my designs at Unisys, to encourage later re-use.


-=-=-=-=-=-=-=-=-=-=-=-=-
 Chris Papademetrious
 Data Fusion Laboratory
 Drexel University
 Philadelphia, PA
-=-=-=-=-=-=-=-=-=-=-=-=-