Hardware Design supporting Ada

Hardware Design supporting Ada

[Shark8]

In the Ada IR thread an interesting sub-discussion regarding specialized hardware came up; some of the HW mentioned were:
* The Rational R-1000
—— https://en.wikipedia.org/wiki/Rational_R1000
—— http://datamuseum.dk/wiki/Rational/R1000s400
—— http://www.somethinkodd.com/oddthinking/category/geek/software-development/rat1000/
—— http://repository.cmu.edu/cgi/viewcontent.cgi?article=1141&context=sei
* The Intel iAPX 432
—— https://en.wikipedia.org/wiki/Intel_iAPX_432
—— http://www.brouhaha.com/~eric/retrocomputing/intel/iapx432/cs460/
—— http://bitsavers.trailing-edge.com/pdf/intel/iAPX_432/172283-001_Reference_Manual_for_the_Intel_432_Extensions_to_Ada_Dec81.pdf
* The Rekursiv
—— https://en.wikipedia.org/wiki/Rekursiv
—— http://web.archive.org/web/20070607072521/http://www.erg.abdn.ac.uk/research/projects/rekursiv.html
—— http://www.slideshare.net/sebrose/rekursiv

In addition to this, I've been doing some work looking into balanced-ternary computers -- like this: http://practicaldev.herokuapp.com/buntine/the-balanced-ternary-machines-of-soviet-russia and this: http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.139.3198&rep=rep1&type=pdf -- which indicate that it is possible and implementable w/ current fabrication processes.

Further, [balanced] ternary provides some interesting properties; if, for example, we define {1, 0, -1} as {greater-than, equal, less-than} respectively then we can have a JUMP instruction that takes this single Trit comparison result and three offsets and take care of ALL the JUMP combinations in binary instruction-sets with one instruction. Moreover, if we define ((x,x,x),(x,x,x),(x,x,x)) as a "Byte" then a single Byte may be used to describe any binary operation. (e.g. Result = Byte_Value(A)(B).)

Taking these properties into consideration we could reduce something like
if A AND B then
statements_1;
elsif A XOR B then
statements_2;
else
statements_3;
end if;

to a single compare and a single jump via the following byte/table ((-1,1,-1)(1,0,1)(-1,1,-1)) with the jump populated w/ offset-values appropriately set.

I may be able to get into some chip manufacturing (I have a few contacts, and some family involved in the industry) -- there's also a university nearby which may be interested (HEAVY tech and math emphases; students needing senior-projects, professors possibly needing research topics, etc) and my particular State (in the US) is looking to stimulate its economy, so obtaining a grant is not out-of-the-question.

However, this is all moot w/o having a clear vision WRT to what the end-product should be. What I have in mind now is a ternary computer with a co-processor of 9 'cores' where each core is a 3-stack stack-machine; this -- http://fpgacpu.ca/stack/Second-Generation_Stack_Computer_Architecture.pdf -- illustrates a few stack-machines, one of which has a predicted sustained execution rate of 2400 MIPS.... but I honestly have little idea of what I could do in-hardware to support Ada, which I'd like to do.

What's everyone on comp.lang.ada's suggestions, insights, and advice on the topic?

Re: Hardware Design supporting Ada

[Niklas Holsti]

On 16-12-11 22:55 , Shark8 wrote:
> In the Ada IR thread an interesting sub-discussion regarding
> specialized hardware came up; some of the HW mentioned were:
> * The Rational R-1000
   ...
> * The Intel iAPX 432
    ...
> * The Rekursiv

Did they mention the Nokia MPS-10:

http://dl.acm.org/citation.cfm?id=989799&dl=ACM&coll=DL&CFID=874929794&CFTOKEN=55213355

http://computer-programming-forum.com/44-ada/596b4e2f57763ce6.htm

> In addition to this, I've been doing some work looking into
> balanced-ternary computers ...
 > Further, [balanced] ternary provides some interesting properties;
 > if,for example, we define {1, 0, -1} as {greater-than, equal,
 > less-than} respectively then we can have a JUMP instruction
 > that takes this single Trit comparison result and three offsets
 > and take care of ALL the JUMP combinations in binary instruction
 > -sets with one instruction.

Then you will be able to implement the original FORTRAN "arithmetic 
IF-statement" very efficiently, it being of the form

    IF (expr) 100, 200, 300

which would pass control to the label 100 if the expression in the 
parenthesis is negative, to 200 if it is zero, and to 300 if it is positive.

However, I don't see how such an instruction would help Ada, in particular.

-- 
Niklas Holsti
Tidorum Ltd
niklas holsti tidorum fi
       .      @       .

Re: Hardware Design supporting Ada

[Shark8]

On Sunday, December 11, 2016 at 2:15:18 PM UTC-7, Niklas Holsti wrote:
> 
> Did they mention the Nokia MPS-10:
> 
> http://dl.acm.org/citation.cfm?id=989799&dl=ACM&coll=DL&CFID=874929794&CFTOKEN=55213355
> 
> http://computer-programming-forum.com/44-ada/596b4e2f57763ce6.htm

No, but thank you for the information there!
It looks really interesting -- the MPS-10 along w/ the R-1000 makes it seem like while a considerable effort, HW (and OS) designed for (and programmed in) Ada is a good choice for reliability and maintainability.

> > In addition to this, I've been doing some work looking into
> > balanced-ternary computers ...
>  > Further, [balanced] ternary provides some interesting properties;
>  > if,for example, we define {1, 0, -1} as {greater-than, equal,
>  > less-than} respectively then we can have a JUMP instruction
>  > that takes this single Trit comparison result and three offsets
>  > and take care of ALL the JUMP combinations in binary instruction
>  > -sets with one instruction.
> 
> Then you will be able to implement the original FORTRAN "arithmetic 
> IF-statement" very efficiently, it being of the form
> 
>     IF (expr) 100, 200, 300
> 
> which would pass control to the label 100 if the expression in the 
> parenthesis is negative, to 200 if it is zero, and to 300 if it is positive.
> 
> However, I don't see how such an instruction would help Ada, in particular.

That's true, it /would/ have a more natural mapping to FORTRAN in this case. But, OTOH, Ada's always been of the mindset that the compiler should handle little optimizations like that. (On a semi-related note, the implementation of ternary search-trees would be simple.)

You, and others here, might be interested in this manual on the iAPX 432's proposed extensions to Ada:
http://bitsavers.trailing-edge.com/pdf/intel/iAPX_432/172283-001_Reference_Manual_for_the_Intel_432_Extensions_to_Ada_Dec81.pdf

These extensions mapped to and "conveniently expose[s] the concepts and capabilities of the iAPX 432."