Re: Expected bytes per sloc (semicolons) performance

[Steffen Huber <steffen.huber@gmx.de>]

"David B. Littell" wrote:
> Robert Dewar wrote:
> > "Jeff Creem" <jeff@thecreems.com> wrote:
> > > As for RISC/CISC.... One sometimes ends up with slightly larger code on a
> > > RISC than
> > > CISC machine but this probably has almost as much to do with mandatory nops,
> > >  missed delayed branch opportunities and alignment requirements as it does
> > > with
> > > the straight RISC/CISC issues.
> >
> > This is a misleading assessment. First of all most modern
> > RISC machines do not have mandatory nops etc, so you are
> > really talking about old style architectures here.
> >
> 
> Both MIPS (including MIPS32) and ARM processors provide a branch delay
> slot which may or may not be useful to the compiler.

I don't know much about the MIPS architecture, but are you sure about the
ARM? AFAIK, there is no such thing as a branch delay slot. Branches are
(after flushing the pipeline of course) taken directly.

[snip]
> I guess I'm not sure what a "modern" RISC is - each of the "big three"
> (MIPS, ARM, PowerPC) is haunted by legacy grodiness.

Oh come on. The ARM is surely the cleanest commercially available
processor architecture - at least until they added the THUMB extensions...

[snip]

Steffen

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