Re: Expected bytes per sloc (semicolons) performance

["David B. Littell" <davidl@intercom.com>]

Robert Dewar wrote:
> 
> "Jeff Creem" <jeff@thecreems.com> wrote in message news:<_hRp7.7630$ot.1153235@typhoon.ne.mediaone.net>...
> > As for RISC/CISC.... One sometimes ends up with slightly larger code on a
> > RISC than
> > CISC machine but this probably has almost as much to do with mandatory nops,
> >  missed delayed branch opportunities and alignment requirements as it does
> > with
> > the straight RISC/CISC issues.
> 
> This is a misleading assessment. First of all most modern
> RISC machines do not have mandatory nops etc, so you are
> really talking about old style architectures here.
> 

Both MIPS (including MIPS32) and ARM processors provide a branch delay
slot which may or may not be useful to the compiler.  And the MIPS still
has all those nasty pipeline hazards which definitely require nops to
negate.

I guess I'm not sure what a "modern" RISC is - each of the "big three"
(MIPS, ARM, PowerPC) is haunted by legacy grodiness.  This seems
especially true of the MIPS - the canonical "drunken frat boy" 4th-year
student project. 

;-)


Dave