Re: AI12-0218: What is the portable representation clause for processing IETF packets on little-endian machines?

["Dan'l Miller" <optikos@verizon.net>]

On Thursday, May 10, 2018 at 7:30:43 PM UTC-5, Paul Rubin wrote:
> … it's intended to specify actual memory layout.

vis a vis

> That is a poor way to handle network byte order …

How does specifying “actual memory layout“ not include the topic of byte order?  Endianness is quite honestly the ultimate very first topic in an ISA's definition of “actual memory layout”, either at processor engineering-time or (in bi-endian processors) at PCB engineering-time of pulling a pin high or low.  Endianness even predates word size:  even before software choses to write or read a 16- or 32- or 64-bit integer, its endianness in predetermined beforehand (months or years or decades prior to software's johnny-come-lately decision of word size on which to operate).

Btw, what is nonactual memory layout or actual nonmemory layout or actual memory nonlayout?  I have no idea what the word actual is meaning there or what actual’s presence/absence means.  It would seem that “memory layout” and “actual memory layout” mean exactly the same thing.  And the layout of words and bytes in memory includes their endian order.  (And to Randy's concerns about front-end implementation forcing layout of memory instead of intra-processor registers, there is no such thing as layout of nonmemory (i.e., registers within a processor) because registers do not have addresses, and hence lack endianness of which byte is at the lower-valued address).