Re: Disallowing Pre-Defined Operations

[Paul Graham <pgraham@cadence.com>]

Tucker Taft wrote:
> 
> "Charles H. Sampson" wrote:
> > ...
> > >You'll have to post the exact code if we're to understand what's going
> > >on there (all of the ops declared, and the supposedly ambiguous
> > >statement).  And the error message.
> >
> >      O. K., here's an example.  It's not meant to meaningful, just to
> > show the problem, although I hope that the name for the integer variable
> > suggests how it could be used meaningfully.  This example has been
> The techniques using discriminants are unsatisfactory in my view,
> and too "heavy."  VHDL has the notion of "units" built into the language,
> and its approach should probably be evaluated.

In VHDL units are mainly used for type TIME.  Things get complicated
when you
try to map the physical world onto unit data types.  For instance:

    type time is ...
    type distance is ...
    type velocity is ...
    type acceleration is ...
    type mass is ...

    function "/"(x : distance; y : time) return velocity;
    function "/"(x : velocity; y : time) return acceleration;
    function "*"(x : mass; y : acceleration) return force;
    function "*"(x : force; y : distance) return work;
    ...

Anyway, you can see that the set of units and possible operations
between units
grows very quickly.  I wonder how big a complete physical types package
would
be (complete enough to represent all the equations in a physics or
electonics
textbook for instance)?

Paul