Re: Software reuse

[Erik Jessen <Erik.Jessen@tus.ssi1.com>]

P. Cnudde VH14 (8218) wrote:
> 
> Hello,
> 
> First of all I want to say that the point of this mail is not
> to start endless Ada vs C/C++ discussions, but to have an open
> minded talk about Reuse and the influence of the language on reuse.
> 
> A lot of people talk about reuse but does anybody have experience
> with a company wide reuse system. Not only different development
> teams but also different locations should be supported.
> <snip>
> 
> PS. Does anybody in comp.lang.vhdl tried real reuse using VHDL.
> (That's the language I am most interested in)
> I'll post to all the original newsgroups once, then only post to comp.lang.vhdl.
For VHDL, from what I understand most companies have a structural problem: normally
the designers building the original blocks get positive reviews for getting chips out the 
door as fast as possible, not for spending time making modules that could be reused by other 
groups.

As a result, many companies are not seeing any value from 'reuse' because, while it is a 
good global thing, it isn't smart (from a personal point of view) for anyone in the company 
to work on it.

Change what gets people bonus money, and you'll see reuse happen a lot.

Some practical notes:

1) My company builds almost all of its chips as full-custom CMOS or BiCMOS; we do
	extensive reuse of layouts and schematics, in something that normally people
	don't think of when they say 'reuse'.

2) I think the only practical way to get reuse to happen is to have a separate modelling
	group that either develops reusable blocks from the ground up, or takes blocks
	built by other groups, and "packages" them with documentation, etc. to make
	them reusable.  You need people to have simple goals.  For designers, it should
	be "make it fast, make it right".  For library people, it should be "make it
	reusable".

3) At my previous employer, the DA group built up examples of how to run a complete
	methodology, using very small chips.  This was done using Make, SCCS and UNIX
	scripts.  Designers would either copy the methodology directly, or use it aas
	a template to develop their own.  I think VHDL code reuse will wind up somewhat
	like this.