* new DARPA initiative: optimizing compiler to logic-gates+PCB target
@ 2018-06-30 15:50 Dan'l Miller
2018-07-02 16:34 ` Shark8
0 siblings, 1 reply; 3+ messages in thread
From: Dan'l Miller @ 2018-06-30 15:50 UTC (permalink / raw)
https://www.eetimes.com/document.asp?doc_id=1333422#msgs
What the Electronics Resurgence Initiative (ERI) describes seems to be somewhere in the vicinity of Ada*+VHDL**+SPICE***+ATP****.
* e.g., for at least algorithmic description and data-structure/record-layout description, and perhaps general front-end/optimizing-backend architecture of bringing the concepts of a software compiler to ASIC/FPGA+PCB hardware
** e.g., for digital-logic description
*** e.g., for analog-electronics modeling, especially on the PCB
**** e.g., automated theorem prover, for automated transformation in lifter, lateral, and lowering directions
$100 million bet is on the table at the DARPA casino.
(Around AD2000 or so give or take a few years, Shlaer-Mellor world thought this was going to be their space to dominate. Their vacuum/void is someone else's to fill nowadays.)
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: new DARPA initiative: optimizing compiler to logic-gates+PCB target
2018-06-30 15:50 new DARPA initiative: optimizing compiler to logic-gates+PCB target Dan'l Miller
@ 2018-07-02 16:34 ` Shark8
2018-07-03 14:19 ` Dan'l Miller
0 siblings, 1 reply; 3+ messages in thread
From: Shark8 @ 2018-07-02 16:34 UTC (permalink / raw)
On Saturday, June 30, 2018 at 9:50:29 AM UTC-6, Dan'l Miller wrote:
> https://www.eetimes.com/document.asp?doc_id=1333422#msgs
>
> What the Electronics Resurgence Initiative (ERI) describes seems to be somewhere in the vicinity of Ada*+VHDL**+SPICE***+ATP****.
>
> * e.g., for at least algorithmic description and data-structure/record-layout description, and perhaps general front-end/optimizing-backend architecture of bringing the concepts of a software compiler to ASIC/FPGA+PCB hardware
>
> ** e.g., for digital-logic description
>
> *** e.g., for analog-electronics modeling, especially on the PCB
>
> **** e.g., automated theorem prover, for automated transformation in lifter, lateral, and lowering directions
>
> $100 million bet is on the table at the DARPA casino.
>
> (Around AD2000 or so give or take a few years, Shlaer-Mellor world thought this was going to be their space to dominate. Their vacuum/void is someone else's to fill nowadays.)
Hm, this rather sounds a lot like my idea for a fully integrated HW/SW IDE.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: new DARPA initiative: optimizing compiler to logic-gates+PCB target
2018-07-02 16:34 ` Shark8
@ 2018-07-03 14:19 ` Dan'l Miller
0 siblings, 0 replies; 3+ messages in thread
From: Dan'l Miller @ 2018-07-03 14:19 UTC (permalink / raw)
On Monday, July 2, 2018 at 11:34:22 AM UTC-5, Shark8 wrote:
> On Saturday, June 30, 2018 at 9:50:29 AM UTC-6, Dan'l Miller wrote:
> > https://www.eetimes.com/document.asp?doc_id=1333422#msgs
> >
> > What the Electronics Resurgence Initiative (ERI) describes seems to be somewhere in the vicinity of Ada*+VHDL**+SPICE***+ATP****.
> >
> > * e.g., for at least algorithmic description and data-structure/record-layout description, and perhaps general front-end/optimizing-backend architecture of bringing the concepts of a software compiler to ASIC/FPGA+PCB hardware
> >
> > ** e.g., for digital-logic description
> >
> > *** e.g., for analog-electronics modeling, especially on the PCB
> >
> > **** e.g., automated theorem prover, for automated transformation in lifter, lateral, and lowering directions
> >
> > $100 million bet is on the table at the DARPA casino.
> >
> > (Around AD2000 or so give or take a few years, Shlaer-Mellor world thought this was going to be their space to dominate. Their vacuum/void is someone else's to fill nowadays.)
>
> Hm, this rather sounds a lot like my idea for a fully integrated HW/SW IDE.
Yes, I think so. I share this with c.l.a to show how your idea is the dawn of a new era (and imperative-machine-code-only targets are so 20th-century).
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2018-06-30 15:50 new DARPA initiative: optimizing compiler to logic-gates+PCB target Dan'l Miller
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