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From: kilgallen@eisner.decus.org (Larry Kilgallen)
Subject: Re: aliased & packed?
Date: 1997/05/13
Date: 1997-05-13T00:00:00+00:00	[thread overview]
Message-ID: <1997May13.154714.1@eisner> (raw)
In-Reply-To: EA4nII.803@world.std.com


In article <EA4nII.803@world.std.com>, bobduff@world.std.com (Robert A Duff) writes:

> Is this really true?  I mean, if you access one byte at the start of a
> word (using byte instructions on the 21164), then won't the next seven
> be sitting there in the cache waiting for you?

Good point.  I don't know what they have in there, but probably they
have that.  Of course registers are still faster than cache.

> And it seems like more than a couple of instructions to shift and mask
> an 8-byte word (I mean, using 21064 instructions only), in the case
> where the byte you want is dynamic (i.e. you're indexing randomly into
> an array of bytes -- on the other hand, most array accesses are probably
> sequential).

From what I have seen (several years ago), the register-to-register
instructions on Alpha look quite weird but many of them have clever
uses in such operations.  The instruction set was designed with heavy
input from compiler writers.

Larry Kilgallen




  reply	other threads:[~1997-05-13  0:00 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
1997-05-11  0:00 aliased & packed? tmoran
1997-05-11  0:00 ` Robert Dewar
1997-05-11  0:00   ` Tom Moran
1997-05-12  0:00     ` Robert Dewar
1997-05-12  0:00       ` Robert A Duff
     [not found]         ` <1997May13.065907.1@eisner>
1997-05-13  0:00           ` Robert A Duff
1997-05-13  0:00             ` Larry Kilgallen [this message]
1997-05-14  0:00             ` Richard Kenner
1997-05-13  0:00           ` Robert Dewar
  -- strict thread matches above, loose matches on Subject: below --
1997-05-09  0:00 Tom Moran
1997-05-09  0:00 ` Stephen Leake
1997-05-09  0:00   ` Tom Moran
1997-05-10  0:00 ` Robert Dewar
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