Re: Portable memory barrier?

[Robert Eachus <rieachus@comcast.net>]

On Friday, May 5, 2017 at 10:23:45 PM UTC-4, Jere wrote:
 
> Are there any Ada language constructs that can help?

No, but you don't need the help you think you need.  On modern, superscalar CPUs, you may have the assignment to the buffer and the index operation occurring as part of the same clock cycle.  Then the writes (to memory if memory locations are assigned) will occur in the order required by the ISA (for x86, what you require). For some RISC processors a fence will need to occur as part of that bundle of instructions, but trust the compiler for that.

If the read of the circular buffer is occurring possibly on a different CPU core which shares one or more cache levels, the instructions to make a location Volatile will be ignored by the CPU.  The compiler will mark the location, and the CPU will keep track of the type of memory, but Volatile does not cause writes to main memory. What will happen instead is that the cache coherency subsystem will insure that any accesses by CPU cores, GPUs, disk drives, or whatever will see a virtual location--which can move about--but all reads and writes will occur in sequence.

Didn't you ever wonder why modern CPUs have billions of transistors?  It is to keep things like this straight.  By the way, it can be the case that the first of two successive writes (with no intervening reads) will be eliminated, and/or additional reads may be added.  More to the point, if you cause an interrupt, the CPU will put that CPU core in some state consistent with memory.  Well, where a cache flush will create such a state in memory.  Without a cache flush, the CPU only cares that what it sees through the cache--and write pipes--is consistent.