From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,251afb8f1c322bf0,start X-Google-Attributes: gid103376,public From: Simon Wright Subject: Caching & Annex C.6 Date: 1999/09/03 Message-ID: #1/1 X-Deja-AN: 520970383 X-NNTP-Posting-Host: pogner.demon.co.uk:158.152.70.98 X-Trace: news.demon.co.uk 936446604 nnrp-07:9380 NO-IDENT pogner.demon.co.uk:158.152.70.98 Organization: At Home Newsgroups: comp.lang.ada X-Complaints-To: abuse@demon.net Date: 1999-09-03T00:00:00+00:00 List-Id: In C.6 the AARM says 16 For a volatile object all reads and updates of the object as a whole are performed directly to memory. 16.a Implementation Note: This precludes any use of register temporaries, caches, and other similar optimizations for that object. We've been having an argument as to precisely what sort of "cache" we're talking about here. Is it the CPU cache? does this imply that an implementation must force a cache write-through for volatile objects? My personal view is that the existence or otherwise of the cache is transparent and that all that's required is that the write doesn't go to registers. But then why does the AARM mention cache? Are there (multi-processor, presumably) systems where you would have to force a write-through to get the proper effect? Do Ada implementations on such systems have to do that? -- Simon Wright Work Email: simon.j.wright@gecm.com Alenia Marconi Systems Voice: +44(0)1705-701778 Integrated Systems Division FAX: +44(0)1705-701800