From: Simon Wright <simon@pogner.demon.co.uk>
Subject: Re: Caching & Annex C.6
Date: 1999/09/05
Date: 1999-09-05T00:00:00+00:00 [thread overview]
Message-ID: <x7vg10t2ov4.fsf@pogner.moho> (raw)
In-Reply-To: 7qss9f$a19$1@nnrp1.deja.com
Robert Dewar <robert_dewar@my-deja.com> writes:
> Machines with non-coherent caches always have a way of
> signalling selected data as being non-cachable, forcing
> access to a shared memory
Oh, that's good. Can anyone name a typical machine of this type? (so I
know when to start worrying)
> (well let's say, that's true
> of shared memory machines).
Of course if it didn't have shared memory you wouldn't care .. I
suppose
next prev parent reply other threads:[~1999-09-05 0:00 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-09-03 0:00 Caching & Annex C.6 Simon Wright
1999-09-05 0:00 ` Robert Dewar
1999-09-05 0:00 ` Simon Wright [this message]
1999-09-07 0:00 ` David Kristola
1999-09-08 0:00 ` Robert Dewar
1999-09-08 0:00 ` David Kristola
1999-09-08 0:00 ` Robert Dewar
1999-09-09 0:00 ` Memory mapped registers (was Re: Caching & Annex C.6) David Kristola
1999-09-09 0:00 ` Robert Dewar
1999-09-14 0:00 ` Memory mapped registers (was Re: Cachi David Kristola
1999-09-14 0:00 ` Robert Dewar
1999-09-15 0:00 ` David Kristola
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