From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=ham autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 107f24,582dff0b3f065a52 X-Google-Attributes: gid107f24,public X-Google-Thread: 109fba,582dff0b3f065a52 X-Google-Attributes: gid109fba,public X-Google-Thread: 103376,bc1361a952ec75ca X-Google-Attributes: gid103376,public X-Google-Thread: 1014db,582dff0b3f065a52 X-Google-Attributes: gid1014db,public X-Google-ArrivalTime: 2001-08-03 03:20:03 PST Path: archiver1.google.com!newsfeed.google.com!newsfeed.stanford.edu!newsfeeds.belnet.be!news.belnet.be!oleane.net!oleane!nnrp.oleane.net!not-for-mail From: Reivilo Snuved Newsgroups: comp.lang.ada,comp.lang.c,comp.lang.c++,comp.lang.functional Subject: Re: How Ada could have prevented the Red Code distributed denial of service attack. Followup-To: comp.lang.ada Date: 03 Aug 2001 12:15:42 +0200 Organization: In Reverse Sender: devuns@buzet Message-ID: References: <9kc355$ri0$1@nh.pace.co.uk> <9kcdli$24o$1@nh.pace.co.uk> NNTP-Posting-Host: gauntlet-fr.aonix.fr X-Trace: s1.read.news.oleane.net 996833747 7615 62.161.92.253 (3 Aug 2001 10:15:47 GMT) X-Complaints-To: abuse@oleane.net NNTP-Posting-Date: Fri, 3 Aug 2001 10:15:47 +0000 (UTC) X-Newsreader: Gnus v5.7/Emacs 20.4 Xref: archiver1.google.com comp.lang.ada:11184 comp.lang.c:71861 comp.lang.c++:79616 comp.lang.functional:7250 Date: 2001-08-03T12:15:42+02:00 List-Id: "Marin David Condic" writes: > In the second place the "Operand Error" they refer to is *not* a standard > Ada exception and I and others familiar with the report don't know where the > writers extracted this from. However, given the reference to a 64 bit Float > converting to a 16 bit integer and having some familiarity with the > Mil-Std-1750a microprocessor that was the target machine ... Bzzt. The target machine for Ariane-5 was (and still is) a 68k-series. Operand Error referred to a FPU exception. -- Olivier Devuns | Aonix: http://www.aonix.com