From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-0.5 required=5.0 tests=BAYES_00,INVALID_MSGID, PP_MIME_FAKE_ASCII_TEXT autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII X-Google-Thread: 103376,71b19e01eae3a390 X-Google-Attributes: gid103376,public From: David Brown Subject: Re: Context switching (was: delay until and GNAT) Date: 1999/05/11 Message-ID: #1/1 X-Deja-AN: 476616558 Sender: davidb@opus.davidb.org References: <7gpukr$s82$1@nnrp1.dejanews.com> <7grkbb$cee$1@nnrp1.deja.com> <7grvka$lc5$1@nnrp1.deja.com> <7h1e10$drg$1@nnrp1.deja.com> <3736e102@eeyore.callnetuk.com> <7h83ag$o8$1@nnrp1.deja.com> <7h9cgs$c862@ftp.kvaerner.com> X-Complaints-To: abuse@pacbell.net X-Trace: typhoon-sf.snfc21.pbi.net 926435969 216.103.8.60 (Tue, 11 May 1999 08:19:29 PDT) Organization: David Brown Services NNTP-Posting-Date: Tue, 11 May 1999 08:19:29 PDT Newsgroups: comp.lang.ada Date: 1999-05-11T00:00:00+00:00 List-Id: >>>>> On Tue, 11 May 1999 15:41:21 +0200, "Tarjei Tj�stheim Jensen" said: > Robert Dewar wrote : >>> [:2:] Many processor architectures today provide built-in >>> support for (normal) context switching, so that the operating >>> system will usually have very little to do with the speed of >>> these context switches. Switches can generally be achieved >>> within a few dozen memory clock cycles (typically >>> out-of-cache), which will be, for most modern microcomputers, >>> in the ballpark of 1 microsecond (+/-1oom). >> >> Can you say what processor architectures you have in mind here? >> Certainly none of the ones that GNAT is commonly used on ... >> The context switch on the x86 in particular is horribly slow, >> and one would like to avoid it in a high efficiency x86 exec > This is from memory, so it might not be accurate: > The transputer and the ARM. > The ARM has a complete register set available for interrupt handling so you > don't have to save and restore the user mode register. At least on the ARM cores I've used, there isn't a complete register set available. There is a special kind of interrupt known as a fast interrupt. It has a subset of registers available for it. Seems to me to be the kind of thing a small piece of assembly would use, probably not that useful for high level. Dave Brown