>>>>> On Tue, 11 May 1999 15:41:21 +0200, "Tarjei Tj�stheim Jensen" <tarjei.jensen@kvaerner.no> said:

> Robert Dewar wrote :

>>> [:2:]  Many processor architectures today provide built-in
>>> support for (normal) context switching, so that the operating
>>> system will usually have very little to do with the speed of
>>> these context switches.  Switches can generally be achieved
>>> within a few dozen memory clock cycles (typically
>>> out-of-cache), which will be, for most modern microcomputers,
>>> in the ballpark of 1 microsecond (+/-1oom).
>> 
>> Can you say what processor architectures you have in mind here?
>> Certainly none of the ones that GNAT is commonly used on ...
>> The context switch on the x86 in particular is horribly slow,
>> and one would like to avoid it in a high efficiency x86 exec

> This is from memory, so it might not be accurate:

> The transputer and the ARM.

> The ARM has a complete register set available for interrupt handling so you
> don't have to save and restore the user mode register.

At least on the ARM cores I've used, there isn't a complete register
set available.  There is a special kind of interrupt known as a fast
interrupt.  It has a subset of registers available for it.  Seems to
me to be the kind of thing a small piece of assembly would use,
probably not that useful for high level.

Dave Brown