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From: "Dmitry A. Kazakov" <mailbox@dmitry-kazakov.de>
Newsgroups: comp.lang.ada
Subject: Re: Portable memory barrier?
Date: Mon, 8 May 2017 23:09:44 +0200
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Date: 2017-05-08T23:09:44+02:00
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On 2017-05-08 21:18, Robert Eachus wrote:

> So the CPU can, and normally will, move the counter update before
> the  data write. The CPU wants to merge two writes to the same cache line
> when possible. Obviously, it won't wait for another write of the counter
> or buffer, but if they are present in the reorder buffers, the CPU will
> do what it can to merge them. (The first one goes into the write pipe,
> but the CPU noticed that it will need that value for the associated data
> write. So it pulls a copy out of the write buffer, while leaving the
> original write in place. If the next update becomes available while the
> index is still in the write pipe, the CPU will cancel the original
> write, or change the value to be written. (Depends on the particular
> hardware. Also the CPUs may keep a copy in a renamed register, or it may
> rely on the copy in the write pipe. Depends on the timing, and on the
> size of the register.)

This strategy does not prevent reordering writes:

    FIFO (Write_Index + 1) := Element;
    Write_Index := Write_Index + 1;

into

    Write_Index := Write_Index + 1;
    FIFO (Write_Index) := Element;

which would be a bug.

-- 
Regards,
Dmitry A. Kazakov
http://www.dmitry-kazakov.de