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From: "Dmitry A. Kazakov" <mailbox@dmitry-kazakov.de>
Newsgroups: comp.lang.ada
Subject: Re: Portable memory barrier?
Date: Mon, 8 May 2017 23:09:40 +0200
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Date: 2017-05-08T23:09:40+02:00
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On 2017-05-08 22:29, Niklas Holsti wrote:
> On 17-05-08 19:22 , Dmitry A. Kazakov wrote:
>
> [snip]
>
>> I don't see anything there what would prevent CPU from changing the
>> order of accesses to two *independent* memory locations when only the
>> program logic ties them nothing else. Well, except that there is no
>> obvious reason why it would like to change that order.
>
> I quote from an earlier post of mine in this thread:
>
> Just as in C, volatile accesses in Ada are guaranteed to occur in the
> order and number written in the source code and executed in the
> "standard" order [moreover, this includes all tasks in the program]:
>
> RM C.6 (16/3): All tasks of the program (on all processors) that read or
> update volatile variables see the same order of updates to the
> variables.

This is ambiguous. Does it read as:

A. Order of updates per volatile variable

B. Order of updates to the set of all volatile variables

B is sufficient, A is not. Depending on the implementation A may imply B 
or not.

-- 
Regards,
Dmitry A. Kazakov
http://www.dmitry-kazakov.de