From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=unavailable autolearn_force=no version=3.4.4 Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!aioe.org!.POSTED!not-for-mail From: "Dmitry A. Kazakov" Newsgroups: comp.lang.ada Subject: Re: Portable memory barrier? Date: Mon, 8 May 2017 18:22:49 +0200 Organization: Aioe.org NNTP Server Message-ID: References: <0fc56bf7-1cfa-4776-9c47-a573db315c5f@googlegroups.com> NNTP-Posting-Host: BYuA7L7MRjuLLjcoGHOBxw.user.gioia.aioe.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-Complaints-To: abuse@aioe.org User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 X-Notice: Filtered by postfilter v. 0.8.2 Xref: news.eternal-september.org comp.lang.ada:46701 Date: 2017-05-08T18:22:49+02:00 List-Id: On 2017-05-08 17:56, Robert Eachus wrote: > One sentence summary: The CPU will play lots of tricks behind your > back, but in such a way you can pretend your code works as you intended. > (Er, after you get the bugs out.) > > On Monday, May 8, 2017 at 3:45:26 AM UTC-4, Dmitry A. Kazakov wrote: > >> I don't believe either of the sequences can get reordered by the CPU, >> but it is only belief and common sense. > > Silly rabbit, Trix are for kids. Oops, silly programmer, common > sense has nothing to do with modern CPUs. [...] > Is any of this important to a high-level language programmer? Not > really, unless they are working in hard real time. (Which I did.) If you > program in assembler, or more likely work on a compiler back-end, > knowing which instructions fit together is important. Even more > important is coding so that an instruction that references a new cache > line in memory is followed by as many instructions as possible that > don't use that value. Some times you run into cases where you want to > take advantage of write combining or some other trick involving the > write pipe--but today, smart compiler optimization is about accesses to > main memory and not much else. I don't see anything there what would prevent CPU from changing the order of accesses to two *independent* memory locations when only the program logic ties them nothing else. Well, except that there is no obvious reason why it would like to change that order. Wikipedia provides a more simple example of the problem: https://en.wikipedia.org/wiki/Memory_barrier The case of a lock-free FIFO is different because it involves index and array element. For practical use when the buffer size is > 1 there cannot be any problem. Yet the question stands. In particular, which Ada primitives may ensure safe implementations of lock-free structures when no protected objects used. -- Regards, Dmitry A. Kazakov http://www.dmitry-kazakov.de