From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=unavailable autolearn_force=no version=3.4.4 Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!news.eternal-september.org!.POSTED!not-for-mail From: Simon Clubley Newsgroups: comp.lang.ada Subject: Re: Oberon and Wirthian languages Date: Tue, 22 Apr 2014 12:25:53 +0000 (UTC) Organization: A noiseless patient Spider Message-ID: References: <1ljwj8f.1wqbhvuabsdw1N%csampson@inetworld.net> <51c7d6d4-e3be-44d5-a4ce-f7e875345588@googlegroups.com> <%J32v.70539$kp1.45343@fx14.iad> <8761m535e4.fsf_-_@ludovic-brenta.org> Injection-Date: Tue, 22 Apr 2014 12:25:53 +0000 (UTC) Injection-Info: mx05.eternal-september.org; posting-host="e458ff8b81bc0c159989eb0e36c6e372"; logging-data="20366"; mail-complaints-to="abuse@eternal-september.org"; posting-account="U2FsdGVkX19Gz003abhpT6dlSS8FRMBSRMOlaU5dKtc=" User-Agent: slrn/0.9.8.1 (VMS/Multinet) Cancel-Lock: sha1:C/0CMXDvoTuDCDcqFU1Xu7qPBNc= Xref: news.eternal-september.org comp.lang.ada:19492 Date: 2014-04-22T12:25:53+00:00 List-Id: On 2014-04-22, Simon Wright wrote: > Simon Clubley writes: > >> Thank you. It was not at all 100% clear from the RM if Ada offered the >> _guarantee_ that if you had, say, 3 components in a record assignment >> for a atomic bitfield record, that the record assignment would be treated >> as one atomic operation instead of 3 atomic operations (one for each >> component). > > Are there CPUs that offer bit-field atomicity? Single bits, maybe. And > what about the fact that these are probably to memory-mapped I/O, and > the device registers may only offer byte/word/longword access? Actually, yes, it's quite common to have a small part of memory which is bit addressable on some 8-bit microcontrollers. However, that isn't the concern here. In general memory mapped I/O you have to do a register read/modify bit field/register write sequence in units of the register size. Consider a atomic record with 3 bit fields called A, B and C. Now consider a Ada record assignment statement which sets the values of the 3 bit fields. The question is how is the assignment to the 3 bit fields turned into code ? Is it something like this (which is how it looks in C with masks): ldr r2, [r3, #register_offset] -- Load device register contents into r2 -- r3 contains device base address orr r2, r2, #1 -- Set bit field A to 1 {Additional code here to modify bitfields B and C} str r2, [r3, #register_offset] -- Write all changes to device register at once or is the Ada compiler allowed to do this: ldr r2, [r3, #register_offset] orr r2, r2, #1 -- Set bit field A to 1 str r2, [r3, #register_offset] -- Update bit field A only ldr r2, [r3, #register_offset] {Code here to modify bitfield B} str r2, [r3, #register_offset] -- Update bit field B only ldr r2, [r3, #register_offset] {Code here to modify bitfield C} str r2, [r3, #register_offset] -- Update bit field C only Ie: performs a atomic update of each bit field, but treats each component as a different update operation. Some devices _require_ the first option in order to work correctly and it wasn't clear from reading the Ada 95 RM that it was _guaranteed_ a assignment to a atomic bit field record would result in code which looked like the first option above. You also then have additional issues around wanting to, say, update bit fields B and C at the same time while preserving the current value of bit field A (which is where my "atomic using" suggestion comes in for a C replacement language). Simon. -- Simon Clubley, clubley@remove_me.eisner.decus.org-Earth.UFP Microsoft: Bringing you 1980s technology to a 21st century world