From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=ham autolearn_force=no version=3.4.4 X-Google-Thread: 103376,99210dd26e04d959 X-Google-NewGroupId: yes X-Google-Attributes: gida07f3367d7,domainid0,public,usenet X-Google-Language: ENGLISH,ASCII-7-bit Path: g2news1.google.com!news4.google.com!feeder.news-service.com!94.75.214.39.MISMATCH!aioe.org!not-for-mail From: tmoran@acm.org Newsgroups: comp.lang.ada Subject: Re: Loops and parallel execution Date: Thu, 27 Jan 2011 23:01:54 +0000 (UTC) Organization: Aioe.org NNTP Server Message-ID: References: NNTP-Posting-Host: J4HSNf9Eqj44wTz1J3b8lQ.user.speranza.aioe.org X-Complaints-To: abuse@aioe.org X-Notice: Filtered by postfilter v. 0.8.2 X-Newsreader: Tom's custom newsreader Xref: g2news1.google.com comp.lang.ada:16756 Date: 2011-01-27T23:01:54+00:00 List-Id: > Finally, like Dmitry, I'm skeptical about fine-grained parallelism buying > much. Unless there is specific architectural support (something that doesn't > exist in commonly used processors -- and especially in commonly used target > OSes/RTOSes), the management overhead will kill any savings on "small" What about the SIMD (vector) instructions in Intel CPUs? Or is that better done by simply calling their optimized, CPU capability detecting, libraries?