From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: f43e6,b87849933931bc93 X-Google-Attributes: gidf43e6,public X-Google-Thread: fac41,b87849933931bc93 X-Google-Attributes: gidfac41,public X-Google-Thread: 103376,b87849933931bc93 X-Google-Attributes: gid103376,public X-Google-Thread: 1108a1,b87849933931bc93 X-Google-Attributes: gid1108a1,public From: dewar@merv.cs.nyu.edu (Robert Dewar) Subject: Re: Assembler most efficient??? (was Re: What is wrong with OO ?) Date: 1997/01/11 Message-ID: #1/1 X-Deja-AN: 209147378 references: <5a0niaINNlda@topdog.cs.umbc.edu> <32C43AC8.24E2@sn.no> <32C557F6.532C@rase.com> <5aa0eo$thd@krusty.irvine.com> <5aadbr$ad8@masters0.InterNex.Net> <32D64433.41C6@wi.leidenuniv.nl> <32D6C18B.30A8@calfp.com> organization: New York University newsgroups: comp.lang.eiffel,comp.lang.ada,comp.object,comp.software-eng Date: 1997-01-11T00:00:00+00:00 List-Id: Richie said "Part of the difficulty compilers have with generating good code is that CPUs are being designed by people who coded in assembler and never had to write a compiler." Do you really have evidence of this? What machines are you talking about? I know quite a bit about the design of the common processor chips around, and I really cannot think of one case where the scenario you present above rings true. On the contrary, for example, the design of the MIPS chip was done with input from compiler considerations all along the way. In some sense the whole business of pipelined RISC architecture is intimately wound up with compiler considerations. I can think of some examples in the past where instruction sets have been designed with far too much naive input from high level language and compiler considerations, but none of them seem to have survived into the modern RISC era.