From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,99ab4bb580fc34cd X-Google-Attributes: gid103376,public From: dewar@cs.nyu.edu (Robert Dewar) Subject: Re: Q: access to subprogram Date: 1996/07/10 Message-ID: #1/1 X-Deja-AN: 168181815 references: <4rb9dp$qe6@news1.delphi.com> <4re2ng$t7u@wdl1.wdl.loral.com> <4rud55$5b0@fu-berlin.de> <4rvo07$bbl@goanna.cs.rmit.edu.au> organization: Courant Institute of Mathematical Sciences newsgroups: comp.lang.ada Date: 1996-07-10T00:00:00+00:00 List-Id: Richard said "Ah, but - if a procedure at lexical level N - directly encloses a procedure at lexical level N+1 - which is passed as a parameter all that has to be copied into the parent's activation record is D[1:N] whose size is known at compile time. The child (or the child's wrapper) needs to allocate space to hold the old values of D[1:N] when it is entered." Sure, this is the well known scheme that was used in the original Algol-60 compiler, and was used frequenly early on, and is almost never used now (although as I mentioned in an earlier note, it is what Intel implements in their hardware - the ENTER instruction). The reason that this loses to static links is that unconditionally you end up copying the display whether you need it or not. In the case of static links, you only climb the chain (once per procedure if a reasonable optimizer is in use) if it is needed. With the scheme above, you have a huge chain of procedures that never do any up level references copying around large displays if the nesting depth is deep, just so that someone in the future might be able to reference one element of this display. I wonder who designed this feature at Intel? Someone who knew a bit, but not really enough, about how to deal with up level displays. The ENTER instruction is an instruction that should never ever be used on any of the Intel x86 arcitectures. Even the version with a zero count is highly dubious if you look at the timings. A perfect example of silly CISC design.