From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 109fba,df854b5838c3e14 X-Google-Attributes: gid109fba,public X-Google-Thread: 103376,df854b5838c3e14 X-Google-Attributes: gid103376,public X-Google-Thread: 10db24,fec75f150a0d78f5 X-Google-Attributes: gid10db24,public X-Google-Thread: 1014db,df854b5838c3e14 X-Google-Attributes: gid1014db,public From: dewar@cs.nyu.edu (Robert Dewar) Subject: Re: ANSI C and POSIX (was Re: C/C++ knocks the crap out of Ada) Date: 1996/04/10 Message-ID: #1/1 X-Deja-AN: 146826867 references: <4kb2j8$an0@solutions.solon.com> <4kbrt5$k3h@mulga.cs.mu.OZ.AU> <4kcer3$mi4@solutions.solon.com> <4kdnvq$3n8@mulga.cs.mu.OZ.AU> <4kgmgu$jm@galaxy.ucr.edu> organization: Courant Institute of Mathematical Sciences newsgroups: comp.lang.ada,comp.lang.c,comp.lang.c++,comp.edu Date: 1996-04-10T00:00:00+00:00 List-Id: "Are you sure that this is possible on the machines that you'd like your program to run on? On many of today's RISC chips, after all, floating point exceptions are asynchronous: you have no way of knowing which instruction caused the problem." Actually, some modern RISC chips effectively do not generate floating-point exceptions. The IEEE 754 (floating-point) standard does NOT require this capability. An example is the POWER architecture, where you can only get floating-point exceptions by disconnecting the pipeline and slowing down ALL code drastically. This mode is intended only or debugging, not for production use. It seems quite reasonable in fact to consider designing floating-point feature sets with no capability of asyncrhonous exceptions at all.