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Newsgroups: comp.lang.ada
Date: Tue, 3 Jan 2017 12:50:13 -0800 (PST)
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Subject: Re: Interfacing Ada With Full Runtime Directly to Electronic Chips
From: Shark8 <onewingedshark@gmail.com>
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Xref: news.eternal-september.org comp.lang.ada:33028
Date: 2017-01-03T12:50:13-08:00
List-Id: <comp.lang.ada>

On Tuesday, January 3, 2017 at 1:34:31 PM UTC-7, Dmitry A. Kazakov wrote:
> On 2017-01-03 19:02, Shark8 wrote:
> > On Tuesday, January 3, 2017 at 3:34:33 AM UTC-7, Dmitry A. Kazakov wrot=
e:
> >> On 2017-01-03 06:33, Shark8 wrote:
> >>
> >>> That's really interesting, because the system I want to do
> >>> [ultimately] is a ternary computer -- for which tri-state logic is a
> >>> perfect fit.
> >>
> >> Out of curiosity, why tri-state logic and not full four-state one?
> >> Tri-state is incomplete in some operations (e.g. in implication).
> >
> > The completeness of the logic-system depends on which logic-system
> > is  being used -- there are several for three-valued logic -- but it is=
 a
> > non-issue because you can use full Boolean logic (e.g.) by defining 0 t=
o
> > be True and =C2=B11 to be False (i.e. using inverse-logic).*
>=20
> [...]
>=20
> I see, it is just a ternary system and not logic in the sense of lattice=
=20
> and inference, like {False, True, Unknown}.

You can model True/False/Unknown -- just map each value to one of {1,0,J}, =
obviously.

But how would a lattice & inference system look? Esp. at the gate-level.