From mboxrd@z Thu Jan  1 00:00:00 1970
X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me
X-Spam-Level: 
X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM
	autolearn=unavailable autolearn_force=no version=3.4.4
X-Received: by 10.43.135.4 with SMTP id ie4mr15689143icc.1.1395336821086;
 Thu, 20 Mar 2014 10:33:41 -0700 (PDT)
Path: 
 border1.nntp.dca.giganews.com!nntp.giganews.com!ur14no10710639igb.0!news-out.google.com!dd7ni92igb.0!nntp.google.com!peer01.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!post01.iad.highwinds-media.com!fx30.iad.POSTED!not-for-mail
From: Shark8 <OneWingedShark@gmail.com>
User-Agent: Mozilla/5.0 (Windows NT 6.1; Win64; x64;
 rv:31.0) Gecko/20100101 Thunderbird/31.0a1
MIME-Version: 1.0
Newsgroups: comp.lang.ada
Subject: Re: Augusta: An open source Ada 2012 compiler (someday?)
References: <zpudnYzhb9cIB7TO4p2dnAA@giganews.com>
 <mopWu.87082$fr7.34510@fx20.fr7>
In-Reply-To: <mopWu.87082$fr7.34510@fx20.fr7>
Message-ID: <UDFWu.62053$ac6.46054@fx30.iad>
X-Complaints-To: abuse@teranews.com
NNTP-Posting-Date: Thu, 20 Mar 2014 17:33:40 UTC
Organization: TeraNews.com
Date: Thu, 20 Mar 2014 11:35:37 -0700
X-Received-Bytes: 2433
X-Received-Body-CRC: 1507479095
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
X-Original-Bytes: 2452
Xref: number.nntp.dca.giganews.com comp.lang.ada:185230
Date: 2014-03-20T11:35:37-07:00
List-Id: <comp.lang.ada>

On 19-Mar-14 16:04, Brian Drummond wrote:
> I strongly believe Ada and VHDL users should talk to
> each other more than they do!

Isn't that because VHDL is essentially concerned about hardware and 
[most] programmers are essentially worried about software? -- That said, 
would if be possible/feasible to have a compiler that takes a VHDL 
description of some architecture and Ada source and compile it to run on 
that architecture?

I'm certainly no expert on VHDL, all I really know about it is from 
Wikipedia, but a quick search reveals several PDFs that indicate my 
understanding is not entirely wrong and that this might be possible 
(though 'feasible' and 'desirable' are distinct attributes):

How to design your own CPU on FPGAs with VHDL
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CCgQFjAA&url=http%3A%2F%2Fopencores.org%2Fusercontent%2Cdoc%2C1262702554&ei=VyIrU7yTCZLiqAHs2IHQAw&usg=AFQjCNEN_M7VC32q01YXXOF_VU7lF-Ohbw&sig2=FVTaWxQqZ7d-FpVwMzXnOA&bvm=bv.62922401,d.aWM

Processor Implementation in VHDL
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=3&cad=rja&uact=8&ved=0CDQQFjAC&url=http%3A%2F%2Fpeople.tamu.edu%2F~akshitdayal%2F468%2FMIPS-Implementation.pdf&ei=VyIrU7yTCZLiqAHs2IHQAw&usg=AFQjCNEjFFTyaFtik_fnHvxX-qUzL3xotw&sig2=_W3m4sd-Yj5CptA50GdUqw&bvm=bv.62922401,d.aWM

CPU Project
http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=4&cad=rja&uact=8&ved=0CDsQFjAD&url=http%3A%2F%2Fweb.cecs.pdx.edu%2F~mperkows%2FCLASS_VHDL_99%2Fcpu_project.pdf&ei=VyIrU7yTCZLiqAHs2IHQAw&usg=AFQjCNEupGSBWrUUFEayGWjm6xKtyaeKAQ&sig2=Plj713lv0vUcXuONu8HcKw&bvm=bv.62922401,d.aWM