From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,INVALID_MSGID autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 115aec,f41f1f25333fa601 X-Google-Attributes: gid115aec,public X-Google-Thread: 103376,a3ca574fc2007430 X-Google-Attributes: gid103376,public From: John Howard Subject: Re: Ada and Automotive Industry Date: 1996/11/15 Message-ID: #1/1 X-Deja-AN: 196665064 references: <55ea3g$m1j@newsbf02.news.aol.com> <3280DA96.15FB@hso.link.com><1996Nov6.210957.3070@ole.cdac.com> <5683sk$bsc@news.ccit.arizona.edu> content-type: TEXT/PLAIN; charset=US-ASCII organization: SkyNET Corporation mime-version: 1.0 newsgroups: comp.lang.ada,comp.realtime Date: 1996-11-15T00:00:00+00:00 List-Id: One niche for microcontrollers in automotives is the implementation of a Controller Area Network. ISO 11898 specifies high-speed CAN, and ISO 11519 specifies low-speed CAN. Allen-Bradley is promoting a CAN implementation called DeviceNet. As a personal interest I am studying Philips XA (a 16-bit eXtended Architecture of 80C51 tailored to real-time, multi-tasking, and hardware support for high-level language compilers). Philips plans to release an XA derivative having DeviceNet that is intended for the automotive industry. The XA family is well-suited for using Ada 95. As evidence here's a description from the Philips 1995 XA Data Handbook (IC25): The XA supports: 1. Upward compatibility with the 80C51 architecture. 2. 16-bit fully static CPU with a 24-bit program and data address range. 3. Eight 16-bit CPU registers each capable of performing all arithmetic and logic operations as well as acting as memory pointers. Operations may also be performed directly to memory. 4. Both 8-bit and 16-bit CPU registers, each capable of performing all arithmetic and logic operations. 5. An enhanced instruction set that includes bit intensive logic operations and fast signed or unsigned 16X16 multiply and 32/16 divide. 6. Instruction set tailored for high-level language support. 7. Multi-tasking and real-time executives that include up to 32 vectored interrupts, 16 software traps, segmented data memory, and banked registers to support context switching. 8. Low power operation, which is intrinsic to the XA architecture, includes power-down and idle modes. The XA family provides an upward compatibility path for 80C51 users who need higher performance and 64k or more of program memory. The performance of the XA supports the comprehensive bit-oriented operations of the 80C51 while incorporating support for multi-tasking operating systems and high-level languages. The architecture provides direct support for the concept of a multi-tasking OS by providing two (System/User) priviledge levels for isolation between tasks. High performance, interrupt driven, multi-tasking applications requiring protection are feasible with the XA. The present speed of the XA is 10 to 100 times that of the 80C51. The Special Function Register (SFR) bus provides a common interface for the addition of any new functions to the XA core, thus supplying the means for building a large and varied microcontroller derivative family. The XA is inexpensive enough to compete in the market for high-volume, low-cost applications. [But is Ada 95 well-suited to support the XA family of derivatives? Very much so. One example: the bit level capability of Ada matches perfectly with the hardware of the XA. Likewise the Ada support of tasking, exceptions, and interrupt handling matches with the hardware of the XA. Plus the hierarchical organization of the Ada library can easily accomodate the logical expansion of the XA family of derivatives. Ada 95 supports distributed systems. The system on which a distributed program runs consists of one or more processor nodes and zero or more storage nodes. There will be market opportunities where using multiple XA devices are more cost effective and powerful than using a 32-bit or larger microcontroller solution. A distributed system using DeviceNet as the communication subsystem is most probable. Fundamentally the high level of detail that can be specified with Ada 95 allows for the possibility of highly effective compiling. In the case of the XA, the instruction set has been made powerful and efficient with the addition of several different types of addressing modes. The formats have been chosen to optimize the length and execution speed of those instructions that would be used the most often in critical code. The safety checks of Ada tend to simplify debugging. The XA further simplifies debugging by providing a Trace Mode, and a software breakpoint instruction. Trace Mode supports user-supplied debugger/monitor programs which can single-step through any code, even code in ROM. Only code executing in System Mode can activate or turn off Trace Mode. In conclusion, many features of Ada 95 closely complement the hardware facilities of the XA to aid the goal of reliably controlling complexity.] -- John Howard -- Team Ada Team OS/2 --