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From: karl@grebyn.com (Karl A. Nyberg)
Newsgroups: comp.lang.ada
Subject: Latest SBIR Solicitation Ada Projects
Message-ID: <9005041306.AA02072@grebyn.com>
Date: 4 May 90 13:06:09 GMT
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Organization: The Internet
List-Id: <comp.lang.ada>

Department of the Navy, n90-365:

Title: High Efficiency Ada Compiler

Objective:  Study the feasibility and implement a high efficiency Ada
compiler to minimize system overhead and memory requirements in small, real
time systems.

Description:  Present Ada compilers impose a very large overhead, a factor
of 3 or 4, in terms of operating speed and memory requirements.  Small
volume and/or power limited real-time systems such as those used in airborne
computers cannot function acceptably with such a high overhead, and cannot
presently gain the advantages of Ada.

Phase I Definition and deliverables: A study would investigate the
feasibility of a high efficiency Ada compiler that would execute with
minimal performance degradation and memory requirements, in the range of 16K
to 64K bytes for the total system, application and overhead.  These
requirements are driven by the need to conserve electric power in small
systems with self-contained power sources.

Phase II Definition and Deliverables - A high efficiency Ada compiler would
be written and targeted to modern high performance micorporcessors such as
the Harris RTX2000 Forth engine and/or the Allied Signal 1750A chip.  The
size of the compiler itself is not critical, but the application program and
overhead code must be in the range of 16K to 64K bytes and execute with the
absolute minimum of overhead to conserve electrical power.  Demonstration of
the compiler in an existing airborne computer system, such as the AYK-14,
should be included.

================

Closing date on this solicitation is 2 July 1990.

-- Karl --