From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=ham autolearn_force=no version=3.4.4 X-Google-Thread: a07f3367d7,7b60a2e8329f4e64 X-Google-Attributes: gida07f3367d7,public,usenet X-Google-NewGroupId: yes X-Google-Language: ENGLISH,ASCII-7-bit X-Received: by 10.224.175.65 with SMTP id w1mr5190146qaz.7.1358511843101; Fri, 18 Jan 2013 04:24:03 -0800 (PST) X-Received: by 10.49.58.167 with SMTP id s7mr2003879qeq.5.1358511843047; Fri, 18 Jan 2013 04:24:03 -0800 (PST) Path: k2ni675qap.0!nntp.google.com!p13no1224420qai.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Fri, 18 Jan 2013 04:24:02 -0800 (PST) In-Reply-To: <63e09fad-16f0-468d-9d38-7969aaf3abe9@googlegroups.com> Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=74.69.172.183; posting-account=YkFdLgoAAADpWnfCBA6ZXMWTz2zHNd0j NNTP-Posting-Host: 74.69.172.183 References: <20bda3de-b033-4b4e-8298-2ac47701b814@googlegroups.com> <0169b2ea-30b4-45d1-a4d4-c5841e54b9ad@googlegroups.com> <31facfa1-dae9-47c0-b5af-262e31c1d4f9@googlegroups.com> <63e09fad-16f0-468d-9d38-7969aaf3abe9@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <8a7a9e6f-6f87-44a7-942b-2275a9ecf049@googlegroups.com> Subject: Re: GNAT 4.4.5 Record Bit_Order Endian issues From: awdorrin Injection-Date: Fri, 18 Jan 2013 12:24:03 +0000 Content-Type: text/plain; charset=ISO-8859-1 Date: 2013-01-18T04:24:02-08:00 List-Id: On Thursday, January 17, 2013 5:16:36 PM UTC-5, awdorrin wrote: > This is why I thought the Bit_Order flag was used to fix. > > On Intel, using Bit_Order = System.High_Order_First, > I would have expected to see: 0xcb 0xa0 I had a realization in the shower this morning: The byte and bit ranges used in the specification clause is not describing memory locations, it is describing the location in the CPU register. The Bit_Order flag is being used to describe which end of the CPU register is bit zero. So the 'machine scalar' term that was being used earlier is really refering to the size of the memory access used to load the register. Due to the (byte level) endian differences, it would seem that it is not possible to describe the physical bit locations in memory, since it is the offset in the register that is being described. In order to get the record memory contents ordered the way I want them to be, I'm going to have to play some byte swap games and translate the record memory contents into a 'big endian buffer'. Presumably, if the record contents can be defined in terms of a 32-bit 'machine scalar' - then this endian conversion can be done by starting at 'MyTrkRec'Address' and doing byte swaps on 4-byte (32-bit) groupings. In C I'd simply make a 'uint32_t' pointer to the record address, and loop through till the end of the record doing 'htonl()' calls. But Ada doesn't make things quite so 'easy' ;-) Fixing poorly designed legacy code is really not my favorite thing to do...