Re: Caching & Annex C.6

[dkristol@see-my.sig (David Kristola)]

In article 1@nnrp1.deja.com, Robert Dewar <robert_dewar@my-deja.com> () writes:
>In article <7r1l93$9lq4@svlss.lmms.lmco.com>,
>  dkristol@see-my.sig wrote:
>> I work with real-time embedded systems, and we use pragma
>> Volatile to mark variables that represent (and are located
>> on) memory mapped registers.  The data must be written to
>> the memory mapped register when that code executes.
>> Likewise, many of those registers return values set by
>> hardware, so reads can't come from the cache.
>
>But usually the ensurance of non-caching of these addresses
>will be done at the hardware level, it is not something the
>compiler worries about. The compiler's responsibility is
>simply to issue loads and stores, someone else must make
>sure that the loads and stores work as planned (for example
>on the MIPS one bit of the address space is used to indicate
>cachability). There are machines with different loads and
>stores to control caching, but not many!

True.  Those memory mapped register variables are also
placed at the correct location using the uncached
address in the representation specification.

And after being burned by one compiler, i started using
appropriately sized integers for the register overlay,
and calling unchecked conversion to convert the data
to the register's record structure.  This eliminated
the compiler's optimization which inadvertently read and
wrote bytes on either side of the register.  Those bytes
happened to be parts of other registers, and the hardware
did not handle byte access properly.  That particular bug
took a while to track down.


--djk, keeper of arcane lore & trivial fluff
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