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From: Robert Dewar <robert_dewar@my-deja.com>
Subject: Re: Caching & Annex C.6
Date: 1999/09/08
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Date: 1999-09-08T00:00:00+00:00
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In article <7r1l93$9lq4@svlss.lmms.lmco.com>,
  dkristol@see-my.sig wrote:
> I work with real-time embedded systems, and we use pragma
> Volatile to mark variables that represent (and are located
> on) memory mapped registers.  The data must be written to
> the memory mapped register when that code executes.
> Likewise, many of those registers return values set by
> hardware, so reads can't come from the cache.

But usually the ensurance of non-caching of these addresses
will be done at the hardware level, it is not something the
compiler worries about. The compiler's responsibility is
simply to issue loads and stores, someone else must make
sure that the loads and stores work as planned (for example
on the MIPS one bit of the address space is used to indicate
cachability). There are machines with different loads and
stores to control caching, but not many!


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