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From: dkristol@see-my.sig (David Kristola)
Subject: Re: Caching & Annex C.6
Date: 1999/09/07
Message-ID: <7r1l93$9lq4@svlss.lmms.lmco.com>#1/1
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References: <x7vyaenahw3.fsf@pogner.moho>
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Reply-To: dkristol@see-my.sig
Newsgroups: comp.lang.ada
Date: 1999-09-07T00:00:00+00:00
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In article fsf@pogner.moho, Simon Wright <simon@pogner.demon.co.uk> () writes:
>In C.6 the AARM says
>
>16 For a volatile object all reads and updates of the object as a
>   whole are performed directly to memory.
>
>   16.a Implementation Note: This precludes any use of register
>      temporaries, caches, and other similar optimizations for that
>      object.
>
>We've been having an argument as to precisely what sort of "cache"
>we're talking about here. Is it the CPU cache? does this imply that an
>implementation must force a cache write-through for volatile objects?
>
>My personal view is that the existence or otherwise of the cache is
>transparent and that all that's required is that the write doesn't go
>to registers. But then why does the AARM mention cache?
>
>Are there (multi-processor, presumably) systems where you would have
>to force a write-through to get the proper effect? Do Ada
>implementations on such systems have to do that?


I work with real-time embedded systems, and we use pragma
Volatile to mark variables that represent (and are located
on) memory mapped registers.  The data must be written to
the memory mapped register when that code executes.
Likewise, many of those registers return values set by
hardware, so reads can't come from the cache.


--djk, keeper of arcane lore & trivial fluff
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