From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: * X-Spam-Status: No, score=1.3 required=5.0 tests=BAYES_00,INVALID_MSGID, MSGID_RANDY autolearn=no autolearn_force=no version=3.4.4 X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 103376,71b19e01eae3a390 X-Google-Attributes: gid103376,public From: dennison@telepath.com Subject: Re: Context Switching Date: 1999/05/12 Message-ID: <7hc2lh$513$1@nnrp1.deja.com>#1/1 X-Deja-AN: 476999365 References: <3736e104@eeyore.callnetuk.com> <37383ab3@eeyore.callnetuk.com> <7h9nl5$9hr$1@nnrp1.deja.com> <3738A31D.1013C463@mitre.org> X-Http-Proxy: 1.0 x35.deja.com:80 (Squid/1.1.22) for client 204.48.27.130 Organization: Deja.com - Share what you know. Learn what you don't. X-Article-Creation-Date: Wed May 12 14:19:55 1999 GMT Newsgroups: comp.lang.ada X-Http-User-Agent: Mozilla/4.5 [en] (WinNT; I) Date: 1999-05-12T00:00:00+00:00 List-Id: In article <3738A31D.1013C463@mitre.org>, "Robert I. Eachus" wrote: > > > Actually we have been finding on some modern microprocessors that > the (distributed) overhead of cache misses can dominate other costs. On > others, where the cache is a "physical" cache that does not have to be > invalidated, > this overhead is very small. I don't remember which chips are which > here, but there were some cases where the cache miss overhead tripled > the cost of a thread switch. The "patch" I was talking about in another posting for vxWorks on a PII was basicly the removal of a "write back invalidate cache" instruction (WBINVD). According to Intel, it took about 5 cycles or so on a Pentium and 486, but takes over 2000 on a PII. Yikes! We knew there was a problem when the same code ran *slower* on a PII-400 than on a Pentium 166... -- T.E.D. --== Sent via Deja.com http://www.deja.com/ ==-- ---Share what you know. Learn what you don't.---