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Newsgroups: comp.lang.ada
Date: Mon, 8 May 2017 21:44:28 -0700 (PDT)
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Subject: Re: Portable memory barrier?
From: Robert Eachus <rieachus@comcast.net>
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Xref: news.eternal-september.org comp.lang.ada:46719
Date: 2017-05-08T21:44:28-07:00
List-Id: <comp.lang.ada>

On Tuesday, May 9, 2017 at 12:32:38 AM UTC-4, Robert Eachus wrote:
Did it again, well posted before I was finished editing.  But this time I'm=
 just going to add a few sentences:

When reading x86 rules, understand moves to registers as reads, moves to me=
mory as writes even though they use the same op code.  Oh, and notice that =
the strict ordering on writes is on moves to cache, not on when they get co=
pied back to main memory. Same goes for reads.  Reads and writes of differe=
nt locations can be reordered, reads cannot be moved past reads, writes can=
 not be moved past writes.

The rule on reordering of reads has a big gotcha.  The CPU can speculativel=
y read from a memory location whenever it wants.  But it must not DO anythi=
ng with that data until a real read comes along.  This allows the cache to =
pull in a complete cache line among other things.  And the most important p=
art of not do anything is no interrupts.