From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=unavailable autolearn_force=no version=3.4.4 X-Received: by 10.107.3.98 with SMTP id 95mr4472418iod.98.1494271089450; Mon, 08 May 2017 12:18:09 -0700 (PDT) X-Received: by 10.157.55.133 with SMTP id x5mr814581otb.10.1494271089413; Mon, 08 May 2017 12:18:09 -0700 (PDT) Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!news.eternal-september.org!news.eternal-september.org!feeder.eternal-september.org!news.glorb.com!c26no1536730itd.0!news-out.google.com!x200ni1786itb.0!nntp.google.com!c26no1536726itd.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Mon, 8 May 2017 12:18:09 -0700 (PDT) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:191:8303:2100:5985:2c17:9409:aa9c; posting-account=fdRd8woAAADTIlxCu9FgvDrUK4wPzvy3 NNTP-Posting-Host: 2601:191:8303:2100:5985:2c17:9409:aa9c References: <0fc56bf7-1cfa-4776-9c47-a573db315c5f@googlegroups.com> User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <7b0c08eb-be62-4d14-ae99-cad038ad0a62@googlegroups.com> Subject: Re: Portable memory barrier? From: Robert Eachus Injection-Date: Mon, 08 May 2017 19:18:09 +0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Xref: news.eternal-september.org comp.lang.ada:46708 Date: 2017-05-08T12:18:09-07:00 List-Id: On Monday, May 8, 2017 at 12:22:55 PM UTC-4, Dmitry A. Kazakov wrote: > Yet the question stands. In particular, which Ada primitives may ensure= =20 > safe implementations of lock-free structures when no protected objects us= ed. There are two rules on x86 and AMD64 CPUs that govern: Instructions must be retired in the correct order. (In practice, CPUs retir= e instructions in bunches.) The execution state "seen" by an instruction reflects those instructions wh= ich were retired before it, and only those instructions. In other words, the index update will occur, but the value to be used in th= e data field write will be kept in the original register. This may result = in two or more registers named AX, but that is a detail. Only the appropri= ate version will be visible to any other instruction. So the CPU can, and normally will, move the counter update before the data = write. The CPU wants to merge two writes to the same cache line when possi= ble. Obviously, it won't wait for another write of the counter or buffer, = but if they are present in the reorder buffers, the CPU will do what it can= to merge them. (The first one goes into the write pipe, but the CPU notice= d that it will need that value for the associated data write. So it pulls = a copy out of the write buffer, while leaving the original write in place. = If the next update becomes available while the index is still in the write= pipe, the CPU will cancel the original write, or change the value to be wr= itten. (Depends on the particular hardware. Also the CPUs may keep a copy= in a renamed register, or it may rely on the copy in the write pipe. Depe= nds on the timing, and on the size of the register.) If, and ONLY if, there is an interrupt, and it is due to an instruction wit= h an associated state (usually a cache miss) the CPU will stop in the corre= ct state, no matter how much patching up that requires. (Minimize page fau= lts, but you knew that. ;-) THEN the interrupt will occur. A page fault h= ere is a reference to a memory location which is in the pagefile, not in me= mory. The CPU may get involved in a cache miss, but that process is usuall= y all in hardware and tries to be invisible to the instruction stream. In = other words, the CPU will try to anticipate cache misses, but when it does = so, it won't cause an interrupt, just throw the prefetch away.