From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=unavailable autolearn_force=no version=3.4.4 X-Received: by 10.236.227.162 with SMTP id d32mr6157377yhq.7.1423773530768; Thu, 12 Feb 2015 12:38:50 -0800 (PST) X-Received: by 10.182.68.113 with SMTP id v17mr54401obt.38.1423773530541; Thu, 12 Feb 2015 12:38:50 -0800 (PST) Path: border1.nntp.dca1.giganews.com!border2.nntp.dca1.giganews.com!nntp.giganews.com!j7no165018qaq.1!news-out.google.com!db6ni25585igc.0!nntp.google.com!hl2no15159606igb.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Thu, 12 Feb 2015 12:38:50 -0800 (PST) Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=74.203.194.21; posting-account=bXcJoAoAAAAWI5APBG37o4XwnD4kTuQQ NNTP-Posting-Host: 74.203.194.21 User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <6c8a59ee-d011-4d9f-999b-54cb0d7cf40a@googlegroups.com> Subject: Ravenscar-sfp and interrupt priorities on Cortex-M4 From: Patrick Noffke Injection-Date: Thu, 12 Feb 2015 20:38:50 +0000 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Xref: number.nntp.giganews.com comp.lang.ada:192260 Date: 2015-02-12T12:38:50-08:00 List-Id: Hello, I am porting the GNAT Ravenscar-sfp runtime to work with the TI TM4C MCU, u= sing the STM32F4 implementation as a starting point. I noticed a problem where the interrupt priorities were not correct. I was= setting an interrupt handler's priority to 251, and the runtime converted = it to a PRI value, and when it got converted back to an Interrupt_Priority = it came back as 252. I determined this is because the TM4C MCU only uses the 3 most-significant = bits for the PRI value, where as the runtime implementation assumes 4 bits.= The ARM Cortex-M4 user's guide does not specify the number of bits, only = that the most significant bits shall be used and the unused bits are zeros = when read and writes have no effect (http://infocenter.arm.com/help/topic/c= om.arm.doc.dui0553a/CIHIGCIF.html). The file system-xi-cortexm4-sfp.ads defines Interrupt_Priority range from 2= 41 to 255, and this should be 249 to 255 for the TM4C MCU. Because the ava= ilable range is processor-dependent, this file should probably be renamed t= o something like system-xi-stm32f4.ads and system-xi-tm4c.ads, etc., and th= e appropriate file selected in build-rts.sh. I copied file s-bbbosu-stm32f4.adb to s-bbbosu-tm4c.adb and had to then cha= nge the To_PRI and To_Priority functions to multiply and divide by 32, resp= ectively. I am happy to share my implementation when I have confidence it is working.= Please let me know the best way to share it. I'm fine for it to become a= part of the GNAT release. Please let me know if you agree with my above findings and suggestions. Best regards, Patrick