From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM autolearn=unavailable autolearn_force=no version=3.4.4 X-Received: by 10.107.88.11 with SMTP id m11mr6250548iob.18.1513835758284; Wed, 20 Dec 2017 21:55:58 -0800 (PST) X-Received: by 10.157.14.137 with SMTP id 9mr419886otj.14.1513835758051; Wed, 20 Dec 2017 21:55:58 -0800 (PST) Path: eternal-september.org!reader01.eternal-september.org!reader02.eternal-september.org!feeder.eternal-september.org!paganini.bofh.team!weretis.net!feeder6.news.weretis.net!feeder.usenetexpress.com!feeder-in1.iad1.usenetexpress.com!border1.nntp.dca1.giganews.com!nntp.giganews.com!i6no957725itb.0!news-out.google.com!b73ni3182ita.0!nntp.google.com!g80no963313itg.0!postnews.google.com!glegroupsg2000goo.googlegroups.com!not-for-mail Newsgroups: comp.lang.ada Date: Wed, 20 Dec 2017 21:55:57 -0800 (PST) In-Reply-To: Complaints-To: groups-abuse@google.com Injection-Info: glegroupsg2000goo.googlegroups.com; posting-host=2601:191:8303:2100:4521:c3eb:4ca9:f096; posting-account=fdRd8woAAADTIlxCu9FgvDrUK4wPzvy3 NNTP-Posting-Host: 2601:191:8303:2100:4521:c3eb:4ca9:f096 References: User-Agent: G2/1.0 MIME-Version: 1.0 Message-ID: <609cb46c-3565-483b-a2b0-2b5d2cfda80a@googlegroups.com> Subject: Re: Compiler doesn't respect 'Size for atomic object From: Robert Eachus Injection-Date: Thu, 21 Dec 2017 05:55:58 +0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Xref: reader02.eternal-september.org comp.lang.ada:49563 Date: 2017-12-20T21:55:57-08:00 List-Id: On Wednesday, December 20, 2017 at 4:20:22 PM UTC-5, Simon Wright wrote: > I meant, naturally an integral type. The RM description of the NVIC's > STIR indicates that the IRQ fits in 8 bits; the top 24 bits are reserved > (write as 0). A language lawyer reading: If the hardware specifies that those bit must b= e zero? Then it is definitely a bug. But if all the hardware says is that= the positions are reserved, I would expect the compiler to pass whatever j= unk happened to be in the register. (In other words, move the IRQ as eight= -bits to a register, then pass the register to the hardware.) Should the address of Register in your example be set to 16#E000EF00#? Also= should your type Interrupt_ID be given a size? If so I would expect the n= ew behavior with Interrupt_ID'Size set to 8, and the old behavior when it i= s set to 32. I am certainly not an expert on the Cortex-M CPUs, but as I read the docume= ntation, the STIR is write-only, and the upper 24-bits of the value written= there are ignored. If so, no bug, but probably worth a comment IF the beh= avior of the compiler has changed, not just the bits you are passing..